ASIC Design Verification Engineer | UVM | Exp 8+ Years

Cisco is hiring an ASIC Design Verification Engineer | UVM | Exp 8+ Years in Bengaluru, India. Level rates it ; you can apply on Cisco.

Level's read on this job

Level rates this role Little AI ●○○○: aI is not part of the work.
Tools and skills the posting cites include UVM, System Verilog and Perl.
Level classifies it as a senior role.
Level lists 1,400+ other open roles at Cisco.

AI in this role

Design and verify ASIC subsystems for high-volume platforms at Cisco with a focus on hardware and verification.

UVMSystem VerilogPerlPython

asic-designverificationrtldebugging

Define, design and verify ASIC and ASIC subsystems to be deployed in a range of Cisco platforms. Contribute to a multi-disciplined engineering team to meet the power, performance, and area goals for products. Design, document, and develop ASIC subsystems for release in high volume and quality. Help define the process, methods, and tools for design and implementation of complex developments.

You will contribute to developing Cisco’s product solutions by crafting industry-leading sophisticated chips, with full exposure to all aspects of our systems and applications, including silicon, hardware, software, telemetry, and security.

Specific responsibilities include:
* Architect block, cluster and top-level DV environment infrastructure.
* Develop DV infrastructure from scratch.
* Maintain and improve existing DV environments.
* Develop test plans and tests for qualifying design at block, cluster and higher-level environments with mix of constraint random and advised stimulus.
* Ensure complete verification coverage through implementation and review of code and functional coverage.
* Ensure RTL quality with qualifying the design with Gate Level Simulations on netlist.
* Collaborate closely with designers, architects, and software teams to address and debug issues during post-silicon bring-up, ensuring seamless integration and efficient performance.
* Support testing of design in emulation.
* Lead all aspects of and manage the ASIC bring-up process.

Minimum Qualifications
* Bachelor’s Degree with 7+ years of relevant ASIC design verification experience.
* Masters Degree with 5+ years of relevant ASIC design verification experience.
* Proficient in ASIC verification using UVM/System Verilog.
* Proficient in verifying sophisticated blocks, clusters and top level for ASIC.
* Experience building test benches from scratch, hands on experience with System Verilog constraints, structures and classes.
* Scripting experience with Perl and/or Python.

Preferred Qualifications
* Experience with Forwarding logic/Parsers/P4.
* Experience with Veloce/Palladium/Zebu/HAPS.
* Formal verification (iev/vc formal) knowledge.
* Demonstrated ability on one or more protocols (PCIe, Ethernet, RDMA, TCP).

Why Cisco?

At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.

Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.

We are Cisco, and our power starts with you.

How we rate this

ASIC Design Verification Engineer | UVM | Exp 8+ Years at Cisco rates 10 out of 100 for how much of the daily work is AI. That makes it Little AI (AI Level 1 of 4). The level is about AI in the job, not seniority.

Classification

Little AI. AI is not part of the work.

●●●● Builds AI80 to 100
●●●○ Works on AI60 to 79
●●○○ Uses AI40 to 59
●○○○ Little AI0 to 39

Levels come from how often the tools, models and workflows of the role are named in the posting itself. Read the description and count the AI tools, models and workflows it names.

Key facts

ASIC Design Verification Engineer | UVM | Exp 8+ Years is an open job at Cisco.
Level rates this role AI Level 1 of 4: Little AI.
The role is based in Bangalore, India.
The job was posted on May 14, 2026.
Seniority: senior.
Applications are handled by Cisco. Apply on Cisco

Prepare for this job

Built from this posting and from similar jobs on Level.

Skills and AI tools this role asks for

Asic DesignVerificationRtlDebuggingUVMSystem VerilogPerlPython

Questions you could be asked

Tell me about a project where asic design was part of your work. What did you do?
Tell me about a project where verification was part of your work. What did you do?
Tell me about a project where rtl was part of your work. What did you do?
Tell me about a project where debugging was part of your work. What did you do?
Walk me through how you've used UVM in your day-to-day work.

Adapt your resume

List these exact terms on your resume: Asic Design, Verification, Rtl, Debugging, and UVM. An applicant tracking system matches the wording, not the idea.
Attach one line of real, concrete experience to at least one of them. A tool named with nothing behind it rarely survives a human read.

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