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Cisco

ASIC Design Verification Technical Leader

Cisco is hiring an ASIC Design Verification Technical Leader. Level rates it ; you can apply on Cisco.

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  • Level rates this role Little AI ●○○○: aI is not part of the work.
  • Level classifies it as a senior role.
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AI in this role

This is a hybrid role with four days per week at Cisco’s Yerevan office.

Meet the team

Join a dynamic group dedicated to ensuring robust test infrastructure for cutting-edge hardware solutions. Our team collaborates closely with design and product development teams, playing a pivotal role in the integration and validation of test logic throughout the development lifecycle. With a diverse mix of experienced engineers, the team thrives on innovation, problem-solving, and mutual support. The fast-paced, collaborative environment provides opportunities to learn and grow while working on industry-leading technologies. What’s exciting is the chance to influence product quality and reliability at a foundational level.

Your impact

Drive comprehensive test planning and develop advanced test benches to ensure design integrity. Collaborate with cross-functional teams to integrate and validate test logic at every phase of implementation. Utilize scripting and debugging tools to streamline verification workflows and identify issues efficiently. Apply your expertise to optimize test processes and enhance product quality. Deliver critical verification solutions that directly impact the success and reliability of our products.

Minimum qualifications

  • Bachelor’s or Master’s Degree in Electrical or Computer Engineering or any related field.
  • 7+ years of experience in design verification.
  • Prior experience in test planning based on complex design specifications.
  • Proficiency in testbench development using System Verilog.
  • Debugging experience preferably using DVE and Verdi.
  • Strong scripting skills with at least one of Tcl, Python and Perl.
  • Knowledge of constrained-random verification and functional coverage.
  • Knowledge of ASIC design flow and verification methodologies.

Preferred qualifications

  • UVM and advanced System Verilog knowledge.
  • Knowledge of JTAG protocol.
  • Familiarity with SLM IP and verification strategies.
  • Ability to work effectively in cross-functional teams.
  • Strong analytical and problem-solving skills.
  • Good communication skills and ability to work in a team environment.

Why Cisco?

At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.

Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.

We are Cisco, and our power starts with you.

How we rate this

ASIC Design Verification Technical Leader at Cisco rates 33 out of 100 for how much of the daily work is AI. That makes it Little AI (AI Level 1 of 4). The level is about AI in the job, not seniority.

Classification

Little AI. AI is not part of the work.

  1. ●●●● Builds AI80 to 100
  2. ●●●○ Works on AI60 to 79
  3. ●●○○ Uses AI40 to 59
  4. ●○○○ Little AI0 to 39

Levels come from how often the tools, models and workflows of the role are named in the posting itself. Read the description and count the AI tools, models and workflows it names.

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