ASIC DFT Engineering Technical Leader | ATPG, SCAN, MBIST, JTAG | 12+ years, Bangalore
Cisco is hiring an ASIC DFT Engineering Technical Leader | ATPG, SCAN, MBIST, JTAG | 12+ years, Bangalore in Bengaluru, India. Level rates it ; you can apply on Level.
AI in this role
ASIC DFT Engineering Technical Leader to drive Design-for-Test and quality processes for high-performance networking silicon.
The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. We design the networking hardware for Enterprises and Service Providers of various sizes, the Public Sector, and Non-Profit Organizations across the world. Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio. Come join us and take part in shaping Cisco's ground-breaking solutions by designing, developing and testing some of the most complex ASICs being developed in the industry.
Your Impact:You will be in the Silicon One development organization as an ASIC Implementation Technical Lead with a primary focus on Design-for-Test. You will work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive DFT requirements early in the design cycle. As a member of this team you will also be involved in crafting groundbreaking next generation networking chips. You will help lead to drive the DFT and quality process through the entire Implementation flow and post silicon validation phases with additional exposure to physical design signoff activities.
Key Contributions:
Manages the definition, architecture and design of high performance ASICs
Owns applications or multiple complex functional areas
Oversees reusable code and its applications
Creates re-usable code that promotes efficiencies in new ways
Defines verification strategies
Coordinates with appropriate stakeholders to integrate into PD and DV flows
Owns infrastructure and testing environmens
Leads and designs the building blocks of multiple channels
Applies and drives the design methodology from conception to production
Influences and collaborates with teams to ensure specifications and requirements are met
Leads technical expertise of a physical design function
Interfaces with vendors and design leads on full chip timing closure, PI, and PV
Owns the full electrical planning and specifications of electrical interfaces
Develops multiple solutions, first test vehicles and performs verification and validation
Bachelor's or a Master’s Degree in Electrical or Computer Engineering required with at least 12+ years of experience.
Prior experience with Jtag protocols ( p1500, p1687) , Scan insertion and BIST architectures, including memory BIST and boundary scan.
Prior experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, Test static timing analysis constraints development and timing closure,
Prior experience working with Gate level simulation, including timing based simulations with sdf , debugging with VCS and other simulators.
Post-silicon validation and debug experience; Ability to work with ATE engineers on pattern translation and validation.
Scripting skills: Tcl, Python/Perl.
Preferred Qualifications:
Verilog design experience – developing custom DFT logic & IP integration; familiarity with functional verification
• DFT CAD development – Test Architecture, Methodology and Infrastructure
Why Cisco?
At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.
Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.
We are Cisco, and our power starts with you.
Disclaimer
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- be in direct response to an application you have submitted through the company career site
- begin with screening or an interview
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- be conducted across email, phone, or WebEx
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If you are the target of a recruiting scam, consider filing a report with your local law enforcement authorities. Cisco bears no responsibility, and cannot be held liable, for any claims, damages, expenses, or other inconvenience resulting from or in any way connected to recruiting scams.
How we rate this
ASIC DFT Engineering Technical Leader | ATPG, SCAN, MBIST, JTAG | 12+ years, Bangalore at Cisco rates 0 out of 100 for how much of the daily work is AI. That makes it Little AI (AI Level 1 of 4). The level is about AI in the job, not seniority.
Little AI. AI is not part of the work.
- ●●●● Builds AI80 to 100
- ●●●○ Works on AI60 to 79
- ●●○○ Uses AI40 to 59
- ●○○○ Little AI0 to 39
Levels come from how often the tools, models and workflows of the role are named in the posting itself. Open the description and count.
Prepare for this job
Built from this posting and from similar jobs on Level.
Skills and AI tools this role asks for
Questions you could be asked
- Tell me about a project where asic was part of your work. What did you do?
- Tell me about a project where dft was part of your work. What did you do?
- Tell me about a project where rtl was part of your work. What did you do?
- Tell me about a project where physical design was part of your work. What did you do?
- Tell me about a project where silicon validation was part of your work. What did you do?
Adapt your resume
- List these exact terms on your resume: Asic, Dft, Rtl, Physical Design, and Silicon Validation. An applicant tracking system matches the wording, not the idea.
- Attach one line of real, concrete experience to at least one of them. A tool named with nothing behind it rarely survives a human read.
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