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ASIC Engineer - Block Level Physical Design Engineer - Armenia - ETR

Cisco is hiring an ASIC Engineer - Block Level Physical Design Engineer - Armenia - ETR. Level rates it ; you can apply on Cisco.

Level's read on this job

  • Little AI ●○○○ is how Level rates this role: aI is not part of the work.
  • The posting mentions Python, Perl and Tcl among its tools and skills.
  • Level classes it as an internship.
  • Cisco has 1,400+ other open roles on Level.
  • Posted within the past week.

AI in this role

Contribute to ASIC and DFT design for hardware platforms powering AI-era infrastructure while learning chip design flows.

pythonperltcl
asic-designdftrtlvlsi

Please note this posting is to advertise potential job opportunities. This exact role may not be open today but could open in the near future. When you apply, a Cisco representative may contact you directly if a relevant position opens.

Meet the Team
The Silicon One team creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organisations globally. Our innovations in silicon, optics, and hardware platforms are shaping the technology industry. We're a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow. Because full product development—from design to qualification to production—is within our team, we’re able to think differently, experiment more, and work quickly. Join us to power the future of the digital world.

 

Your Impact

Contribute to the development of state-of-the-art chips by working on full-chip SCAN/ATPG/JTAG based DFT solutions. Develop automation and productivity scripts using Python, PERL or TCL to streamline the ASIC design cycle and improve engineering efficiency. Collaborate with experienced DFT Engineers to learn and implement and verify efficient test implementations in SoC partitions/macro level and SoC level. Gain hands-on experience with RTL, synthesis, scan insertion and scripting to understand the complete DFT insertion and validation flow. This role allows you to make a tangible impact on silicon that powers infrastructure used by millions of people worldwide.

 

Minimum Qualifications

•    Currently enrolled in a Bachelor’s or Master’s program in Microelectronics,

    VLSI, Electrical/Electronics Engineering, Computer Science, or a related field.

•    Good proficiency in a scripting language such as Python, PERL or TCL.

•    Completed coursework in digital logic and computer architecture fundamentals.

•    Foundational knowledge of MOS devices and semiconductor physics.

•    Academic exposure to introductory VLSI or ASIC design concepts.


Preferred Qualifications

•    Interest in learning industry-standard ASIC design flows and EDA tools.

•    Strong analytical and problem-solving skills applied to hardware design.

•    Ability to thrive and collaborate effectively in a fast-paced engineering environment.

•    Desire to learn about complex SoC interconnects, clocks, resets, and power domains.

•    Willingness to engage in structured onboarding and technical mentorship programs.

Why Cisco? 

At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.

Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. 

We are Cisco, and our power starts with you. 

How we rate this

ASIC Engineer - Block Level Physical Design Engineer - Armenia - ETR at Cisco rates 10 out of 100 for how much of the daily work is AI. That makes it Little AI (AI Level 1 of 4). The level is about AI in the job, not seniority.

Classification

Little AI. AI is not part of the work.

  1. ●●●● Builds AI80 to 100
  2. ●●●○ Works on AI60 to 79
  3. ●●○○ Uses AI40 to 59
  4. ●○○○ Little AI0 to 39

Levels come from how often the tools, models and workflows of the role are named in the posting itself. Read the description and count the AI tools, models and workflows it names.

Prepare for this job

Built from this posting and from similar jobs on Level.

Skills and AI tools this role asks for

Asic DesignDftRtlVlsiPythonPerlTcl

Questions you could be asked

  1. Tell me about a project where asic design was part of your work. What did you do?
  2. Tell me about a project where dft was part of your work. What did you do?
  3. Tell me about a project where rtl was part of your work. What did you do?
  4. Tell me about a project where vlsi was part of your work. What did you do?
  5. Walk me through how you've used Python in your day-to-day work.

Adapt your resume

  • List these exact terms on your resume: Asic Design, Dft, Rtl, Vlsi, and Python. An applicant tracking system matches the wording, not the idea.
  • Attach one line of real, concrete experience to at least one of them. A tool named with nothing behind it rarely survives a human read.

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