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Cisco

ASIC Engineering Lead

Cisco is hiring an ASIC Engineering Lead. Level rates it ; you can apply on Cisco.

Level's read on this job

  • On Level's scale, this role is Little AI ●○○○: aI is not part of the work.
  • Level classes it as a lead role.
  • Cisco has 1,400+ other open roles on Level.

AI in this role

Meet the Team

Join Cisco’s CHG Team in Armenia, a team at the forefront of physical design for the globally recognized Silicon One brand. We specialize in chip-level implementation for innovative networking technology, tackling large-scale design challenges with advanced methodologies and best-in-class tools. Our team is a collaborative group of experts dedicated to redefining the boundaries of what is possible in silicon. By driving the physical implementation of high-complexity silicon, we ensure the performance and reliability of the technology that powers tomorrow’s connectivity. This is an exciting opportunity to work on cutting-edge networking chips in a dynamic, global environment.


Your Impact

Lead the end-to-end physical implementation of high-complexity silicon blocks from RTL to tape-out to ensure production-ready design delivery. Apply deep expertise in synthesis, place-and-route, and timing closure to meet stringent performance, power, and area (PPA) goals. Collaborate with global frontend, IP, and CAD teams to resolve complex implementation challenges and ensure seamless system-level integration. Advance physical design methodologies by leading technical investigations and proposing improvements to streamline development flows. Provide technical direction to peers to foster an innovative engineering environment that delivers impactful networking solutions.

Minimum Qualifications
  • Bachelor's or Master's degree in Electrical Engineering, Computer Science, or a related field.

  • Minimum of 8 years of experience in ASIC design, physical implementation, and verification.

  • Proven expertise in deep submicron CMOS technologies.

  • Extensive knowledge of the full design cycle from RTL to GDSII.

  • Demonstrated mastery in block-level synthesis, place-and-route, and timing closure.

  • Excellent verbal and written communication skills in English.

Preferred Qualifications
  • Direct experience with EM/IR and ESD analysis, including debugging and solution development.

  • Proficiency in scripting languages such as Tcl, Python, or Shell to improve design flow efficiency.

  • Proven ability to mentor team members and foster a collaborative environment.

  • Experience collaborating with global teams and external vendor partners.

Why Cisco?

At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.

Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.

We are Cisco, and our power starts with you.

How we rate this

ASIC Engineering Lead at Cisco rates 33 out of 100 for how much of the daily work is AI. That makes it Little AI (AI Level 1 of 4). The level is about AI in the job, not seniority.

Classification

Little AI. AI is not part of the work.

  1. ●●●● Builds AI80 to 100
  2. ●●●○ Works on AI60 to 79
  3. ●●○○ Uses AI40 to 59
  4. ●○○○ Little AI0 to 39

Levels come from how often the tools, models and workflows of the role are named in the posting itself. Read the description and count the AI tools, models and workflows it names.

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