ASIC Engineering Technical Leader (RTL Design/SOC | 8- 14 Years)

Cisco is hiring an ASIC Engineering Technical Leader (RTL Design/SOC | 8- 14 Years) in Bengaluru, India. Level rates it ; you can apply on Cisco.

Level's read on this job

Little AI ●○○○ is how Level rates this role: aI is not part of the work.
The posting mentions Verilog, SystemVerilog and Python among its tools and skills.
Level classes it as a lead role.
Cisco has 1,500+ other open roles on Level.

AI in this role

Lead ASIC and RTL design for high-performance enterprise and service provider networking chips.

verilogsystemverilogpythoncperl

rtl-designasicsochardware-validation

Meet the Team

Come join us and be part of the Cisco SiliconOne team and take part in crafting Cisco's groundbreaking Enterprise and Service Provider solutions by crafting some of the most complex chips being developed in the industry with the opportunity to get full exposure to all aspects of the systems and applications we build (Silicon, Hardware, Software, telemetry, security, etc). Our group offers a rare combination of a startup culture with the benefits of working for the top tier networking company in the world!

Your Impact

Cisco SiliconOne team is looking for an expert and talented ASIC Engineering Technical Leader. You will have an ASIC design background with hands-on experience in RTL design with in-depth knowledge of ASIC/SoC development cycle, the best industry practices, from specification through tape-out and lab validation, and a proven track record of success in high-performance/high-volume products.

Architectural work: in-depth understanding of the architecture, and identification of problems and solutions.
All aspects of implementation: specification, design, timing-analysis, power-optimization, flow automation, optimization of the logic for low power and area; highlighting issues and standard methodologies for power and area optimization.
Document and improve standard methodologies to make product successful.

Minimum Qualifications

BS/MS and 11+/9+ years respectively of hands-on experience in large-scale, high-performance ASIC
RTL development (Verilog, SystemVerilog, VCS, Spyglass, CDC, Formal verification)
Experienced in system debug and SW/HW bringup, system validation of silicon towards FCS.
Gate-level understanding of RTL and Synthesis
Programming/scripting skills (Python, C, C++, Perl)
Good written/verbal interpersonal skills and leadership skills.

Preferred Qualifications

Worked in architecture and definition of high-scale, high-performance ASICs.
Validated experience in implementation: specification, RTL design, lint, cdc, timing analysis, formal verification, system testing.
Validated experience in flow automation (scripting, Makefiles, etc), and establishing guidelines for the team.
Good interpersonal skills, and validated leadership to accurately describe issues/improvements and lead team for on-time completion.

Why Cisco?

At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.

Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.

We are Cisco, and our power starts with you.

How we rate this

ASIC Engineering Technical Leader (RTL Design/SOC | 8- 14 Years) at Cisco rates 10 out of 100 for how much of the daily work is AI. That makes it Little AI (AI Level 1 of 4). The level is about AI in the job, not seniority.

Classification

Little AI. AI is not part of the work.

●●●● Builds AI80 to 100
●●●○ Works on AI60 to 79
●●○○ Uses AI40 to 59
●○○○ Little AI0 to 39

Levels come from how often the tools, models and workflows of the role are named in the posting itself. Read the description and count the AI tools, models and workflows it names.

Key facts

ASIC Engineering Technical Leader (RTL Design/SOC | 8- 14 Years) is an open job at Cisco.
Level rates this role AI Level 1 of 4: Little AI.
The role is based in Bangalore, India.
The job was posted on August 18, 2026.
Seniority: lead.
Applications are handled by Cisco. Apply on Cisco

Prepare for this job

Built from this posting and from similar jobs on Level.

Skills and AI tools this role asks for

Rtl DesignAsicSocHardware ValidationVerilogSystemVerilogPythonC

Questions you could be asked

Tell me about a project where rtl design was part of your work. What did you do?
Tell me about a project where asic was part of your work. What did you do?
Tell me about a project where soc was part of your work. What did you do?
Tell me about a project where hardware validation was part of your work. What did you do?
Walk me through how you've used Verilog in your day-to-day work.

Adapt your resume

List these exact terms on your resume: Rtl Design, Asic, Soc, Hardware Validation, and Verilog. An applicant tracking system matches the wording, not the idea.
Attach one line of real, concrete experience to at least one of them. A tool named with nothing behind it rarely survives a human read.

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