ASIC Verification Engineer - Clocks

NVIDIA is hiring an ASIC Verification Engineer - Clocks in Bengaluru, India. Level rates it ; you can apply on NVIDIA.

Level's read on this job

On Level's scale, this role is Little AI ●○○○: aI is not part of the work.
The posting mentions System Verilog, UVM and C among its tools and skills.
Level classes it as a senior role.
NVIDIA has 1,800+ other open roles on Level.

AI in this role

Verify complex ASIC clocking and reset logic architectures using industry-standard simulation and verification methodologies.

system-veriloguvmcperlpython

The NVIDIA Clocks Team is looking for an excellent Senior ASIC Verification engineer with extensive experience in Design Verification. The NVIDIA Clocks Team is committed to deliver high-quality clocking and reset logic to various units in SOC automotive and datacenter ASICs. The complexity of the clocks and resets design has increased many folds. This requires sophisticated verification to deliver a bug free clocks design to power our product lines ranging from Data Centers, Consumer graphics to Self-driving cars and the growing field of artificial intelligence. Modern clocking verification solutions need to be innovative, ensure quality in covering the complex design specifications and balance the constraints on infrastructure, re-usability, testing speed and multi-platform support.

What you'll be doing:

Own validation of Clocking structures in Tegra automotive and datacenter products from start to finish, including test plan development, automation, validation flows development, coverage metrics, test execution, bug identification/fix and productization.
Tackle Sophisticated problems and develop a scalable solution that works across platform.
Hands on industry-standard tools and state of the art verification methodologies. This includes coding in System Verilog, UVM, C++, Perl, Python and NVIDIA custom compilers and tools.
Partnering closely with our clocks architecture and design team to validate our clocks design.
Coordinate with internal and external teams across time zones.

What we need to see:

BS or MS in EE/ECE or equivalent experience.
3+ years of relevant industry work experience.
Good understanding of Logic Design and Architecture.
Expertise in industry-standard verification flows like SV constraint random verification, UVM, Formal Verification, Coverage metrics, profiling tools, X prop, etc.
Exposure on block level and system-level verification.
Strong coding skills in System Verilog, scripting languages (Perl/python) and C++.
Ability to collaborate and work with multiple groups.
Prior experience in implementing Test plans for pre-silicon platforms.
Understanding of DFT/IST is optional.

We have some of the most forward-thinking and hardworking people in the world working for us and, due to unprecedented growth, our world-class engineering teams are growing fast. If you are creative, curious, and motivated with real passion for technology, we want to hear from you!

#LI-Hybrid

How we rate this

ASIC Verification Engineer - Clocks at NVIDIA rates 0 out of 100 for how much of the daily work is AI. That makes it Little AI (AI Level 1 of 4). The level is about AI in the job, not seniority.

Classification

Little AI. AI is not part of the work.

●●●● Builds AI80 to 100
●●●○ Works on AI60 to 79
●●○○ Uses AI40 to 59
●○○○ Little AI0 to 39

Levels come from how often the tools, models and workflows of the role are named in the posting itself. Read the description and count the AI tools, models and workflows it names.

Key facts

ASIC Verification Engineer - Clocks is an open job at NVIDIA.
Level rates this role AI Level 1 of 4: Little AI.
The role is based in India, Bengaluru.
The job was posted on October 4, 2026.
Seniority: senior.
Applications are handled by NVIDIA. Apply on NVIDIA

Prepare for this job

Built from this posting and from similar jobs on Level.

Skills and AI tools this role asks for

System VerilogUVMCPerlPython

Questions you could be asked

What's a project where you used System Verilog hands-on?
Walk me through how you've used UVM in your day-to-day work.
What are the limits of C that you've run into, and how did you work around them?
What's a project where you used Perl hands-on?
Walk me through how you've used Python in your day-to-day work.

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List these exact terms on your resume: System Verilog, UVM, C, Perl, and Python. An applicant tracking system matches the wording, not the idea.
Attach one line of real, concrete experience to at least one of them. A tool named with nothing behind it rarely survives a human read.

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