Back-End TD Reliability Lab Manager

Job Description:

As one of the world's largest semiconductor manufacturers, Intel is committed to advancing every aspect of semiconductor technology, from process development and manufacturing to advanced packaging and reliability characterization.
Employees within Intel Foundry are part of a global network spanning technology development, manufacturing, assembly, test, and quality organizations across both front-end silicon and advanced packaging facilities.
You will join the Foundry Lab Network (FLN), a key organization within Foundry Quality, Reliability, and Labs (FQRL), located at Intel's growing Chandler, Arizona site. This site serves as the technology development hub for Intel's most advanced packaging technologies, including Hybrid Bond Interconnect (HBI), Embedded Multi-die Interconnect Bridge (EMIB-T), glass substrates, Foveros, and future advanced packaging innovations.
FLN is actively expanding its laboratory capabilities and capacity to support Intel Foundry's roadmap, enabling faster technology qualification and accelerating development cycles through Quick Turn Monitoring (QTM) solutions that significantly reduce time-to-data.
As the Stress Test and Reliability (STaR) Back-End Laboratory Manager, you will play a critical leadership role within FLN. You will partner closely with Packaging Technology Development, Quality and Reliability, and Failure Analysis teams to establish and enhance laboratory capabilities that support qualification and certification of next-generation packaging technologies and products.
This position offers a unique combination of people leadership, technical problem solving, and organizational strategy. You will lead a team of 7-10 talented engineers, spearhead cross-functional efforts to resolve complex reliability and technology challenges, drive strong quality and operational excellence across the laboratory, and develop a high-performing organization focused on innovation and customer responsiveness.
Our Chandler site offers the opportunity to work at the forefront of semiconductor innovation while enjoying life in the greater Phoenix metropolitan area and the scenic Sonoran Desert, with easy access to world-renowned destinations such as Sedona and the Grand Canyon.

Your key deliverables will include:
• Managing, hiring, coaching, and developing a high-performing team of 8-10 laboratory engineers while building an organization recognized as a destination team within the site.
• Defining and executing the laboratory capability and capacity roadmap to anticipate and meet future customer and technology requirements.
• Ensuring timely and effective response to both internal and external customer needs.
• Developing and implementing a comprehensive strategy to support data collection and qualification requirements for emerging packaging technologies.
• Establishing and advancing Reliability Quick Turn Monitoring (QTM) methodologies to accelerate technology development cycles and decision making.
• Driving a culture of operational excellence, quality leadership, and continuous improvement across the laboratory.
• Leading the laboratory's quality management system development and readiness efforts to achieve ISO 17025 accreditation, including driving effective 8D/root cause analysis for the engineering team.

Behavioral traits:
• Excellent verbal and written communication skills.
• Strong relationship-building, networking, and stakeholder management capabilities.
• Proven ability to influence and drive initiatives across organizational boundaries.
• High emotional intelligence and the ability to lead effectively in a diverse, multicultural environment.
• Ability to perform successfully in dynamic, fast-paced, and evolving environments.
• Demonstrated capability to manage multiple priorities and parallel initiatives in resource-constrained situations

Qualifications:

Qualifications

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
This position is intended for candidates with demonstrated engineering leadership experience and a successful track record of leading teams to solve complex technical challenges.

Minimum Qualifications:
• Master's degree in Electrical Engineering, Mechanical Engineering, Physics, Materials Science, or a related technical discipline.
• 3+ years of engineering management experience in semiconductor packaging, reliability engineering (product or process), test engineering, or validation engineering.
• Demonstrated expertise in process qualification, reliability risk assessment, quality management systems, and quality culture development.

• 2+ years of experience in Hands-on experience on reliability stress and testing.

Preferred Qualifications:
• Knowledge of reliability statistics and life prediction, including accelerated life testing (ALT) and sampling plans (eg AQL/SQL).
• Experience with dynamics testing, especially including shock and vibration, to JEDEC or other standards-based requirements
• Experience with industry standard stress requirements, especially those contained within JESD47 requirements
• Knowledge of advanced packaging assembly process and modules preferably with experience in design rule scaling and/or defect failure modes
• Experience with coordination and auditing of third party stress labs

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Posting Statement:

Position of Trust

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Work Model for this Role

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