CPU Power Delivery Engineer
Intel is hiring a CPU Power Delivery Engineer in Bengaluru, India. Level rates it ; you can apply on Intel.
Level's read on this job
- On Level's scale, this role is Little AI ●○○○: aI is not part of the work.
- The posting mentions Redhawk, Primepower and Kelvin among its tools and skills.
- Level classes it as a senior role.
- Intel has 793 other open roles on Level.
- Posted within the past two weeks.
AI in this role
Own CPU power delivery and power integrity analysis to ensure reliable silicon tapeout.
Job Description:
The Role and Impact As a CPU Power Delivery Engineer, you will play a pivotal role in shaping the future of high-performance computing by driving the physical design implementation of cutting-edge CPU designs. You will ensure robust IR drop, electromigration, and power integrity performance across required operating modes and conditions. This role works across design, physical design, package, and technology teams to reduce risk and support successful silicon delivery. Business group You will join Intel Corporation's CPU design and development team, which is dedicated to engineering world-class computing solutions. This group is at the heart of innovation, delivering high-performance designs that power industry-leading technologies and support Intel's broader mission to advance computing performance and capabilities globally. Key Responsibilities - Own CPU power delivery and power integrity analysis across implementation and signoff, including static and dynamic IR drop, electromigration, and overall power integrity closure. - Develop and drive power grid strategies, power planning, and optimization to meet CPU performance, power, and reliability targets. - Debug and resolve complex power delivery issues in partnership with physical design, package, clock, and RTL teams. - Review and guide floorplan, bump, strap, decap, and grid decisions to improve top-level CPU power robustness. - Track power integrity risks, drive mitigation plans, and support signoff readiness for successful tapeout.Qualifications:
Minimum Qualifications - Bachelor's degree in Electrical Engineering, Electronics Engineering, or related field with 3+ years of hands-on experience OR Master's degree in a relevant field with 2+ years of hands-on experience with strong exposure to CPU or high-performance IP timing closure. - Strong experience in CPU or high-performance IP power delivery, power integrity, or physical design. - Solid understanding of IR drop, electromigration, decap strategy, power grid design, and signoff methodology. - Hands-on experience with industry-standard tools such as RedHawk, PrimePower, Kelvin, and related power integrity or physical design tools. - Proficiency in Tcl and at least one scripting language such as Python or Perl. - Strong debugging, problem-solving, and cross-functional communication skills. Preferred Qualifications - Knowledge of scripting languages like Tcl, Perl, or Python for workflow automation in physical design. - Proven ability to work effectively in dynamic, cross-geographical, and interdisciplinary teams. - Enthusiasm for designing world-class CPUs that drive innovation and empower future technologies. We're eager to welcome talented engineers who are passionate about technology and thrive in collaborative environments. If you're excited to contribute to groundbreaking designs and make an impact, we encourage you to apply today.
Job Type:
Experienced HireShift:
Shift 1 (India)Primary Location:
India, BangaloreAdditional Locations:
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of Trust
N/AWork Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.*
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.How we rate this
CPU Power Delivery Engineer at Intel rates 10 out of 100 for how much of the daily work is AI. That makes it Little AI (AI Level 1 of 4). The level is about AI in the job, not seniority.
Little AI. AI is not part of the work.
- ●●●● Builds AI80 to 100
- ●●●○ Works on AI60 to 79
- ●●○○ Uses AI40 to 59
- ●○○○ Little AI0 to 39
Levels come from how often the tools, models and workflows of the role are named in the posting itself. Read the description and count the AI tools, models and workflows it names.
Prepare for this job
Built from this posting and from similar jobs on Level.
Skills and AI tools this role asks for
Questions you could be asked
- Tell me about a project where power integrity was part of your work. What did you do?
- Tell me about a project where ir drop was part of your work. What did you do?
- Tell me about a project where electromigration was part of your work. What did you do?
- Tell me about a project where physical design was part of your work. What did you do?
- Tell me about a project where cpu design was part of your work. What did you do?
Adapt your resume
- List these exact terms on your resume: Power Integrity, Ir Drop, Electromigration, Physical Design, and Cpu Design. An applicant tracking system matches the wording, not the idea.
- Attach one line of real, concrete experience to at least one of them. A tool named with nothing behind it rarely survives a human read.
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