CPU Senior Timing Engineer

Intel is hiring a CPU Senior Timing Engineer in Bengaluru, India. Level rates it ; you can apply on Intel.

Level's read on this job

Level rates this role Little AI ●○○○: aI is not part of the work.
Tools and skills the posting cites include Primetime, Tempus and Icc2.
Level classifies it as a senior role.
Level lists 798 other open roles at Intel.
The role was posted within the past two weeks.

AI in this role

Drive top-level timing analysis, constraint management, and closure for high-performance CPU designs.

primetimetempusicc2innovustclpythonperl

static-timing-analysisphysical-designtiming-closurecpu-designscripting

Job Details:

Job Description:

The Role and Impact As a CPU Senior Engineer, you will play a pivotal role in shaping the future of high-performance computing by driving the physical design implementation of cutting-edge CPU designs. You will ensure that the design meets frequency, power, and signoff targets across all required modes and corners. This role works across design, block timing, physical design, clocking, and integration teams to resolve critical timing issues, improve timing predictability, and support successful tapeout. Business group You will join Intel Corporation's CPU design and development team, which is dedicated to engineering world-class computing solutions. This group is at the heart of innovation, delivering high-performance designs that power industry-leading technologies and support Intel's broader mission to advance computing performance and capabilities globally. Key Responsibilities - Drive top-level timing analysis and closure for CPU IP across implementation and signoff stages. - Develop, review, and maintain timing constraints, MMMC scenarios, path budgets, and timing exceptions for top-level integration. - Analyze and resolve setup, hold, clock gating, noise, and cross-block timing issues affecting CPU performance targets. - Partner with RTL, block owners, physical design, and clock teams to close critical paths and improve timing convergence. - Ensure correlation between block-level, top-level, and signoff timing environments, and track timing risks against project milestones. - Develop scripts and methodology improvements to automate timing analysis, reporting, and closure efficiency.

Qualifications:

Minimum Qualifications - Bachelor's degree in Electrical Engineering, Electronics Engineering, or related field with 4+ years of hands-on experience OR Master's degree in a relevant field with 3+ years of hands-on experience with strong exposure to CPU or high-performance IP timing closure. - Strong knowledge of static timing analysis, MMMC flows, timing constraints, OCV/derates, crosstalk, and timing exceptions. - Hands-on experience with STA tools such as PrimeTime or Tempus, and familiarity with implementation tools such as ICC2 or Innovus. - Proficiency in Tcl and at least one scripting language such as Python, Perl, or shell. - Strong debugging, problem-solving, and cross-functional communication skills. Preferred Qualifications - Knowledge of scripting languages like Tcl, Perl, or Python for workflow automation in physical design. - Proven ability to work effectively in dynamic, cross-geographical, and interdisciplinary teams. - Enthusiasm for designing world-class CPUs that drive innovation and empower future technologies. We're eager to welcome talented engineers who are passionate about technology and thrive in collaborative environments. If you're excited to contribute to groundbreaking designs and make an impact, we encourage you to apply today.

Job Type:

Experienced Hire

Shift:

Shift 1 (India)

Primary Location:

India, Bangalore

Additional Locations:

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

How we rate this

CPU Senior Timing Engineer at Intel rates 10 out of 100 for how much of the daily work is AI. That makes it Little AI (AI Level 1 of 4). The level is about AI in the job, not seniority.

Classification

Little AI. AI is not part of the work.

●●●● Builds AI80 to 100
●●●○ Works on AI60 to 79
●●○○ Uses AI40 to 59
●○○○ Little AI0 to 39

Levels come from how often the tools, models and workflows of the role are named in the posting itself. Read the description and count the AI tools, models and workflows it names.

Key facts

CPU Senior Timing Engineer is an open job at Intel.
Level rates this role AI Level 1 of 4: Little AI.
The role is based in India, Bangalore.
The job was posted on October 21, 2026.
Seniority: senior.
Applications are handled by Intel. Apply on Intel

Prepare for this job

Built from this posting and from similar jobs on Level.

Skills and AI tools this role asks for

Static Timing AnalysisPhysical DesignTiming ClosureCpu DesignScriptingPrimetimeTempusIcc2

Questions you could be asked

Tell me about a project where static timing analysis was part of your work. What did you do?
Tell me about a project where physical design was part of your work. What did you do?
Tell me about a project where timing closure was part of your work. What did you do?
Tell me about a project where cpu design was part of your work. What did you do?
Tell me about a project where scripting was part of your work. What did you do?

Adapt your resume

List these exact terms on your resume: Static Timing Analysis, Physical Design, Timing Closure, Cpu Design, and Scripting. An applicant tracking system matches the wording, not the idea.
Attach one line of real, concrete experience to at least one of them. A tool named with nothing behind it rarely survives a human read.

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