EDA Workflow Optimization Engineer

NVIDIA is hiring an EDA Workflow Optimization Engineer in Santa Clara, United States. It pays $152k-$242k a year and Level rates it ; you can apply on NVIDIA.

Level's read on this job

Little AI ●○○○ is how Level rates this role: aI is not part of the work.
Level classes it as a senior role.
NVIDIA has 2,700+ other open roles on Level.

AI in this role

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world.

NVIDIA reinvented itself over two decades, inventing the GPU in 1999 to reshape PC gaming and modern computer graphics. As an engineer in our EDA Workflow Optimization team, you will partner closely with our engineering teams worldwide. You will understand workflows covering the full chip design process from inception through study, architecture, design, verification, emulation, layout, packaging, power-on and production. You will then guide teams to improve, and sometimes re-invent those flows. You will enable our engineers to have the best tools on the planet to make the most innovative chips in the world. You will perform investigations to understand flaws and opportunities, construct metrics to continuously measure performance of our flows and services, and other infrastructure. You will work with your team of EDA and software experts to build new infrastructure in an agile, production software environment. You will continuously innovate and enhance scalable, reliable, high performance systems and tools to enable the next generation of chips!

What you’ll be doing:

Work in a diverse team performing fast paced investigations to empower our engineers to develop at the speed of light.
Participate in the full life-cycle of tool development, test, and deployment.
Work closely with other team members and chip engineers to understand and optimize how workflows use the compute and storage environments.
Build metrics that are reliable and easy to use by hundreds of engineers around the world.
Continuously improve our chip development process.
Directly contribute to the overall quality and time to market for our next generation chips.

What we need to see:

Strong experience investigating and debugging complex, multi-discipline problems in a UNIX engineering environment.
Hands-on experience with architectural decisions in technologies (storage, networking, compute) our chip engineers depend on.
Experience with ASIC, VLSI, CAD/EDA or mixed signal design workflow environments.
Hands-on experience with EDA tools.
Experienced in UNIX Systems programming and automation using Python and/or Shell.
Authoritative level usage of UNIX and UNIX utilities.
Excellent planning and communication skills.
Experience in applying data analysis principles and influencing data-driven decisions.
Flexibility/adaptability working in a dynamic environment with changing requirements.
BS in Computer Science or equivalent experience; MS (preferred).
5+yrs of relevant experience.

Ways to stand out from the crowd:

Experience with job schedulers (in particular IBM Spectrum LSF and/or SLURM).
Hands-on experience running GPU-based workloads in a batch computing environment and a deep understanding of distributed system principles.
Strong programming and debugging skills with C/C++, Python, and Perl on UNIX.
A passion for improving engineering productivity and efficiency via data-driven philosophy.

#LI-Hybrid

Your base salary will be determined based on your location, experience, and other objective job-related factors. The expected base salary ranges for this position are:
152,000 USD – 241,500 USD for Level 3; and 184,000 USD – 287,500 USD for Level 4.

You will also be eligible for equity and benefits.

Applications for this job will be accepted at least until November 3, 2026.

This posting is for an existing vacancy.

NVIDIA uses AI tools in its recruiting processes.

NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.

How we rate this

EDA Workflow Optimization Engineer at NVIDIA rates 27 out of 100 for how much of the daily work is AI. That makes it Little AI (AI Level 1 of 4). The level is about AI in the job, not seniority.

Classification

Little AI. AI is not part of the work.

●●●● Builds AI80 to 100
●●●○ Works on AI60 to 79
●●○○ Uses AI40 to 59
●○○○ Little AI0 to 39

Levels come from how often the tools, models and workflows of the role are named in the posting itself. Read the description and count the AI tools, models and workflows it names.