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CERN

Firmware & FPGA Development Engineer (SY-BI-BP-2026-154-GRAP)

CERN is hiring a Firmware & FPGA Development Engineer (SY-BI-BP-2026-154-GRAP) in Geneva, Switzerland. Level rates it ; you can apply on CERN.

Level's read on this job

  • Level rates this role Little AI ●○○○: aI is not part of the work.
  • Level classes it as a mid-level role.
  • CERN has 53 other open roles on Level.

AI in this role

The SY-BI group in CERN's Accelerator Systems Department develops and operates the instruments used to observe particle beams and measure their key properties. These systems are essential to the reliable operation, optimisation, and future development of CERN's accelerator complex.

You will contribute to the development of next-generation beam-position monitoring systems for CERN's injector complex, including the pre-accelerators and Antimatter Decelerator. You will work on innovative high-speed data-acquisition platforms combining fast digitisers with advanced System-on-Chip (SoC) technologies.

This role offers a hands-on opportunity to work at the intersection of digital electronics, embedded systems, real-time signal processing, and accelerator physics. It is particularly suited to people with an interest in FPGA or HDL development, high-speed electronics, embedded software, digital signal processing, instrumentation, or experimental physics.

Your responsibilities:

  • Develop, integrate and test FPGA gateware and embedded SoC firmware for a SoC device.
  • Implement data acquisition and data processing logic and real-time digital signal-processing algorithms.
  • Validate system performance in laboratory and accelerator environments.
  • Perform data analysis in Python.
  • Assist measurement campaigns in the accelerator complex.
  • Collaborate with experienced engineers, physicists, and technicians from different teams across CERN.

Your profile:

  • Experience in digital signal processing.
  • Demonstrated experience with FPGA and SoC.
  • Experience in Software programming (e.g. Python, C++).
  • Demonstrated experience with Xilinx Zynq UltraScale+ MPSoC and/or RFSoC would be an advantage.

Skills:

  • Knowledge of Verilog and SystemVerilog.
  • Knowledge of digital electronics.
  • Knowledge of Python.
  • Spoken and written English, with a commitment to learn French.

Eligibility criteria:

  • You are a national of a CERN Member or Associate Member State.
  • You have a professional background in Electronic Engineering (or a related field) and have either:
    • a Master's degree with 2 to 6 years of post-graduation professional experience;
    • or a PhD with no more than 3 years of post-graduation professional experience.
  • You have never had a CERN fellow or graduate contract before.

Job closing date: 24.11.2026 at 23:59 CEST.

Contract duration: 24 months, with a possible extension up to 36 months maximum.

Working hours: 40 hours per week

Job flexibility: Fully Onsite

Target start date: 01-March-2027

Job reference: SY-BI-BP-2026-154-GRAP

Field of work: Electronics Engineering

Benchmark job: 200050 - Electronics Engineer

Global Benefits

  • A monthly net stipend of either 6372 or 7004 Swiss Francs per month depending on your degree.
  • 30 days of paid leave per year plus 2 weeks annual closure.
  • Coverage by CERN’s comprehensive health insurance scheme (for yourself, your spouse and children), and membership of the CERN Pension Fund.
  • Family, child and infant monthly allowances depending on your individual circumstances.
  • A relocation package (installation grant and travel expenses) depending on your individual circumstances.
  • Possibility to extend your contract up to 36 months.
  • On-the-job and formal training including language classes.

Overview of CERN - Discover a world where the impossible is made possible!

At CERN, the European Organization for Nuclear Research, we are pushing the frontiers of science and technology. Our groundbreaking work brings together not only physicists but also a diverse range of professionals from engineering, technical, scientific, and administrative fields. Together, we foster an environment where innovation and collaboration thrive.

Every day, we face exciting new challenges and opportunities to contribute to cutting-edge research that shapes our understanding of the universe. We meet these challenges through the diverse perspectives within our teams, ensuring every contribution is valued and driving our shared sense of inclusion and purpose. Diversity is a core value of CERN since its foundation, and it remains central to our mission and continued success.

If you are ready to be part of a dynamic, inclusive community pushing the boundaries of knowledge, CERN is the place where your curiosity and skills can thrive. Be part of our mission to uncover what lies at the heart of the universe! TAKE PART!

More information about us, here: careers.cern

How we rate this

Firmware & FPGA Development Engineer (SY-BI-BP-2026-154-GRAP) at CERN rates 21 out of 100 for how much of the daily work is AI. That makes it Little AI (AI Level 1 of 4). The level is about AI in the job, not seniority.

Classification

Little AI. AI is not part of the work.

  1. ●●●● Builds AI80 to 100
  2. ●●●○ Works on AI60 to 79
  3. ●●○○ Uses AI40 to 59
  4. ●○○○ Little AI0 to 39

Levels come from how often the tools, models and workflows of the role are named in the posting itself. Read the description and count the AI tools, models and workflows it names.

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