Formal Verification Engineer - New College Grad 2027
NVIDIA is hiring a Formal Verification Engineer - New College Grad 2027 in Santa Clara, United States. It pays $100k-$167k a year and Level rates it ; you can apply on NVIDIA.
Level's read on this job
- Little AI ●○○○ is how Level rates this role: aI is not part of the work.
- The posting mentions Jasper, Verilog and System Verilog among its tools and skills.
- Level classes it as a junior role.
- NVIDIA has 2,700+ other open roles on Level.
- Posted within the past two weeks.
AI in this role
Own formal verification of RTL units for next-generation chip designs using advanced verification methodologies.
As a Formal Verification Engineer at NVIDIA, you will work in the formal verification team for the industry's leading chips. We are looking for outstanding candidates with knowledge of formal methods. The engineer will own the task of formal verification of RTL units for next generation chip designs. This will involve the candidate having deep knowledge of architectural as well as micro-architectural details of the unit. Ideal candidate must have strong analytical skills, computer architecture background and as well as experience in application of effective verification methodology.
What you will be doing:
- Developing comprehensive FV testplan documents.
- Identifying key behaviors for verification of DUT and creating a verification plan.
- Developing verification environment including environment assumptions, assertions and cover properties in context of the verification plan.
- Applying various FV techniques to proof correctness of digital designs.
- Debugging RTL to identify failure scenarios.
- Developing scripts to automate the verification process.
- Review formal setups and proofs with design and verification teams.
What we need to see:
- BS or MS in CS/CE/EE/Mathematics or equivalent experience.
- Strong analytical skills to solve difficult problems.
- Knowledge/Experience in formal verification techniques.
- Strong knowledge of architectures of CPU/GPU designs and digital logic.
- Understanding of abstraction techniques for effective verification.
- Hands-on experience with HDLs such as Verilog / System Verilog.
- Ability to understand RTL quickly.
- Understanding of temporal logic assertions.
- Preferable experience with Formal Verification Tools (eg. Jasper, IFV, SMV, SPIN)
- Excellent communication skills with ability to work with team members and collaborate effectively.
NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us. Are you creative and autonomous? Do you love the challenge of crafting the highest performance & lowest power silicon possible? If so, we want to hear from you. Come, join our Formal Verification team and help build the real-time, cost-effective computing platform driving our success in this exciting and quickly growing field.
Your base salary will be determined based on your location, experience, and other objective job-related factors. The expected base salary ranges for this position are:100,000 USD – 166,750 USD for Level 1; and 116,000 USD – 189,750 USD for Level 2.
You will also be eligible for equity and benefits.
Applications for this job will be accepted at least until November 3, 2026.This posting is for an existing vacancy.
NVIDIA uses AI tools in its recruiting processes.
NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.How we rate this
Formal Verification Engineer - New College Grad 2027 at NVIDIA rates 0 out of 100 for how much of the daily work is AI. That makes it Little AI (AI Level 1 of 4). The level is about AI in the job, not seniority.
Little AI. AI is not part of the work.
- ●●●● Builds AI80 to 100
- ●●●○ Works on AI60 to 79
- ●●○○ Uses AI40 to 59
- ●○○○ Little AI0 to 39
Levels come from how often the tools, models and workflows of the role are named in the posting itself. Read the description and count the AI tools, models and workflows it names.
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Skills and AI tools this role asks for
Questions you could be asked
- What's a project where you used Jasper hands-on?
- Walk me through how you've used Verilog in your day-to-day work.
- What are the limits of System Verilog that you've run into, and how did you work around them?
- What's a project where you used Ifv hands-on?
- Walk me through how you've used Smv in your day-to-day work.
Adapt your resume
- List these exact terms on your resume: Jasper, Verilog, System Verilog, Ifv, and Smv. An applicant tracking system matches the wording, not the idea.
- Attach one line of real, concrete experience to at least one of them. A tool named with nothing behind it rarely survives a human read.
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