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Cisco

FPGA Design Engineer- Cisco Silicon One

Cisco is hiring an FPGA Design Engineer- Cisco Silicon One. Level rates it ; you can apply on Cisco.

Level's read on this job

  • Level rates this role Little AI ●○○○: aI is not part of the work.
  • Level classifies it as a mid-level role.
  • Level lists 1,400+ other open roles at Cisco.
  • The role was posted in the last few days.

AI in this role

Meet the Team

The Silicon One team creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms are shaping the technology industry. We're a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow. Because full product development—from design to qualification to production—is within our team, we’re able to think differently, experiment more, and work quickly. Join us to power the future of the digital world!.

Your Impact

Lead the FPGA design and development of complex systems supporting next-generation networking devices and AI infrastructure, from initial architecture through implementation, validation, and production. You will take technical ownership of FPGA design activities, including architecture definition, RTL development, simulation, synthesis, timing closure, and hardware validation.

  • Define FPGA specifications, develop and implement RTL designs, and collaborate with Hardware, ASIC, Software, and System engineering teams throughout the product lifecycle.
  • Design and integrate high-speed interfaces and communication protocols, including PCIe, Ethernet, and SerDes. Conduct FPGA bring-up, characterization, debugging, and validation in a lab environment.
  • Identify and resolve complex functional, timing, and integration issues through simulation, debugging tools, and hardware measurements.

Minimum Qualifications

  • B.Sc. in Electrical Engineering or equivalent practical experience.
  • 4+ years of experience as an FPGA design engineer, developing and delivering complex FPGA-based projects.
  • Experience in RTL design using Verilog or SystemVerilog.

Preferred Qualifications

  • Experience with FPGA architecture, design implementation, synthesis, place-and-route, and timing closure.
  • Solid understanding of digital design principles, including clock domain crossing (CDC), timing constraints, synchronization, and reset methodologies.
  • Experience with FPGA simulation, functional verification, and debugging using industry-standard EDA tools.
  • Experience integrating FPGA IP cores, memory interfaces, and communication protocols.

Why Cisco? 

At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.

Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. 

We are Cisco, and our power starts with you. 

How we rate this

FPGA Design Engineer- Cisco Silicon One at Cisco rates 19 out of 100 for how much of the daily work is AI. That makes it Little AI (AI Level 1 of 4). The level is about AI in the job, not seniority.

Classification

Little AI. AI is not part of the work.

  1. ●●●● Builds AI80 to 100
  2. ●●●○ Works on AI60 to 79
  3. ●●○○ Uses AI40 to 59
  4. ●○○○ Little AI0 to 39

Levels come from how often the tools, models and workflows of the role are named in the posting itself. Read the description and count the AI tools, models and workflows it names.

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