GPU Logic Design Engineer

Intel is hiring a GPU Logic Design Engineer in Santa Clara, United States. It pays $106k-$200k a year and Level rates it ; you can apply on Intel.

Level's read on this job

Level rates this role Little AI ●○○○: aI is not part of the work.
The posting mentions System Verilog, rtl design and logic design among its tools and skills.
Level classes it as a mid-level role.
Intel has 860 other open roles on Level.

AI in this role

Develop RTL code and logic designs for next-generation graphics processing units and SoC integration at Intel.

System Verilog

rtl-designlogic-designgpu-architecturehardware-verification

Job Details:

Job Description:

As a GPU Logic Design Engineer, you will play a vital role in developing cutting-edge graphics IPs required for next-generation GPU designs. By leveraging your expertise in logic design and RTL coding, you will contribute to the creation of functional units, GPU IP blocks, and their integration into system-on-chip (SoC) designs.

You will collaborate with diverse teams to define architecture and microarchitecture features, optimizing logic to meet power, performance, area, and timing targets. Your work will directly impact Intel's leadership in graphics technology, enabling innovative solutions for a wide range of applications and products.

Key Responsibilities:

Develop RTL code and implement optimized logic designs for GPU IPs, ensuring alignment with architecture and microarchitecture specifications.
Perform power, performance, area, and timing optimization to meet design goals during physical implementation.
Participate in defining architecture and microarchitecture features for GPU blocks, contributing to innovation and technology leadership.
Execute unit-level verification, debug failing RTL tests, and resolve design issues to achieve correctness, functionality, and robustness at all verification hierarchies.
Utilize formal equivalence verification (FEV) techniques to ensure design accuracy and fidelity across development stages.
Collaborate with SoC customers to ensure seamless and high-quality integration of GPU blocks into full chip designs.
Drive microarchitecture-level enhancements and provide technical documentation to support design and development activities.

Qualifications:

Minimum Qualifications are required to be initially considered for this position.

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field with 4+ or more years of experience in RTL design and logic development with expertise in System Verilog.

Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field with 3+ or more years of experience in RTL design and logic development with expertise in System Verilog.

PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field with 6+ or more months of experience in RTL design and logic development with expertise in System Verilog.

Preferred Qualifications, are in addition to the minimum requirements and are considered a plus factor in identifying top candidates:

Proficiency in low-power design techniques, including UPF coding and debugging.
Experience with static timing analysis and formal equivalence verification (FEV).
Understanding of GPU architecture fundamentals and digital design principles.
Technical proficiency in TCL scripting for design automation tasks.
Demonstrated ability to debug microarchitecture and hardware simulations effectively.
Advanced knowledge of microarchitecture fundamentals and GPU validation methodologies.
Experience with power and performance validation and debugging in large-scale GPU designs.
Strong communication and collaboration skills, with a track record of working in cross-functional teams to solve complex problems.

Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.

Job Type:

Experienced Hire

Shift:

Shift 1 (United States of America)

Primary Location:

US, California, Santa Clara

Additional Locations:

US, California, Folsom

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $105,650.00-200,340.00 USD

The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

How we rate this

GPU Logic Design Engineer at Intel rates 0 out of 100 for how much of the daily work is AI. That makes it Little AI (AI Level 1 of 4). The level is about AI in the job, not seniority.

Classification

Little AI. AI is not part of the work.

●●●● Builds AI80 to 100
●●●○ Works on AI60 to 79
●●○○ Uses AI40 to 59
●○○○ Little AI0 to 39

Levels come from how often the tools, models and workflows of the role are named in the posting itself. Read the description and count the AI tools, models and workflows it names.

Key facts

GPU Logic Design Engineer is an open job at Intel.
Level rates this role AI Level 1 of 4: Little AI.
The listed salary is $106k-$200k a year.
The role is based in US, California, Santa Clara.
The job was posted on September 28, 2026.
Seniority: mid.
Applications are handled by Intel. Apply on Intel

Prepare for this job

Built from this posting and from similar jobs on Level.

Skills and AI tools this role asks for

Rtl DesignLogic DesignGPU ArchitectureHardware VerificationSystem Verilog

Questions you could be asked

Tell me about a project where rtl design was part of your work. What did you do?
Tell me about a project where logic design was part of your work. What did you do?
Tell me about a project where gpu architecture was part of your work. What did you do?
Tell me about a project where hardware verification was part of your work. What did you do?
Walk me through how you've used System Verilog in your day-to-day work.

Adapt your resume

List these exact terms on your resume: Rtl Design, Logic Design, GPU Architecture, Hardware Verification, and System Verilog. An applicant tracking system matches the wording, not the idea.
Attach one line of real, concrete experience to at least one of them. A tool named with nothing behind it rarely survives a human read.

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