GPU Logic Design Engineer

Intel is hiring a GPU Logic Design Engineer in Bengaluru, India. Level rates it ; you can apply on Intel.

Level's read on this job

Little AI ●○○○ is how Level rates this role: aI is not part of the work.
Level classifies it as a junior role.
Level lists 823 other open roles at Intel.
The role was posted within the past week.

AI in this role

Job Details:

Job Description:

The Role and Impact As a DFT Design Engineer, you will play a crucial role in developing and delivering high-quality design-for-test (DFT) solutions for cutting-edge semiconductor products. You will focus on logic design, RTL coding, and simulation, while collaborating on architecture and microarchitecture definitions. Your contributions directly impact product quality and manufacturability by optimizing test coverage, debug efficiency, and production ramp-up, ensuring Intel's leadership in advanced SoC designs. Business group The Data Center Group (DCG) drives innovation in data center technologies to empower businesses and industries globally. As part of this high-impact organization, you will contribute to the development of world-class systems and solutions that support Intel's vision to transform data into actionable insights, enabling scalable, efficient, and secure computing. Key Responsibilities - Develop logic design, RTL coding, and DFT timing closure support for test content generation, including SCAN, MBIST, and BSCAN. - Collaborate on the definition of architecture and microarchitecture features for blocks and subsystems under DFT design. - Create and optimize HVM content for rapid bring-up and production ramp on automatic test equipment (ATE). - Apply strategies, tools, and methods to integrate DFT into RTL and structural code while meeting power, performance, area, and timing goals. - Review verification plans and drive verification of DFT designs to ensure alignment with architecture and microarchitecture specifications. - Resolve RTL test failures and implement corrective measures to ensure design accuracy and feature correctness. - Integrate DFT blocks into functional IP and SoC, supporting SoC customers to ensure seamless integration and high-quality design outcomes. - Collaborate with post-silicon and manufacturing teams to support debug and verification on silicon, documenting learnings for continuous improvement. - Drive high test coverage and develop structural and specific IP tests to achieve quality and defect-per-million (DPM) objectives.

Qualifications:

Minimum Qualifications - Bachelor's degree in Electrical Engineering, Computer Engineering, or related field with 0-1 years of hands-on experience through internships, academic projects, coursework, or training. - OR a Master's degree in Electrical Engineering, Computer Engineering, or related field with no prior professional experience. - Proficiency in RTL coding and simulation tools (e.g., SystemVerilog, VCS). - Foundational understanding of DFT methodologies such as SCAN, MBIST, and BSCAN. Preferred Qualifications - Strong problem-solving skills and a collaborative mindset. - Familiarity with SoC architecture and microarchitecture features. - Knowledge of test equipment tools and strategies for production ramp-up. - Passion for innovation and commitment to delivering high-quality solutions. Join us in shaping the future of semiconductor technology. Your contributions will drive the scalability and reliability of Intel's products, while fostering personal growth and career development in an inspiring environment.

Job Type:

College Grad

Shift:

Shift 1 (India)

Primary Location:

India, Bangalore

Additional Locations:

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

How we rate this

GPU Logic Design Engineer at Intel rates 35 out of 100 for how much of the daily work is AI. That makes it Little AI (AI Level 1 of 4). The level is about AI in the job, not seniority.

Classification

Little AI. AI is not part of the work.

●●●● Builds AI80 to 100
●●●○ Works on AI60 to 79
●●○○ Uses AI40 to 59
●○○○ Little AI0 to 39

Levels come from how often the tools, models and workflows of the role are named in the posting itself. Read the description and count the AI tools, models and workflows it names.