Hardware Design Engineer (Temporary position)

Intel is hiring a Hardware Design Engineer (Temporary position) in Guadalajara, Mexico. Level rates it ; you can apply on Intel.

Level's read on this job

On Level's scale, this role is Little AI ●○○○: aI is not part of the work.
Tools and skills the posting cites include Cadence, hardware design and schematic capture.
Level classifies it as a mid-level role.
Level lists 860 other open roles at Intel.

AI in this role

Architect and design electrical hardware solutions and PCB layouts for Intel's data center group.

Cadence

hardware-designschematic-capturepcb-layoutcircuit-design

Job Details:

Job Description:

The Role and Impact

We welcome you to be part of a team that values innovation, collaboration, and growth, where your contributions will make a meaningful impact on the future of data-centric computing solutions.

This role offers you the opportunity to contribute to impactful projects within Intel's Data Center Group, focusing on technical and innovative responsibilities. As a valued team member, you will play a pivotal role in driving solutions that enhance Intel's hardware initiatives, ensuring growth and advancement in cutting-edge technologies. Your day-to-day work will involve diverse technical tasks, providing hands-on experience in a fast-paced, dynamic environment.

Business Group

The Data Center Group (DCG) is at the forefront of driving Intel's data-centric strategy, delivering solutions that power the infrastructure supporting cloud computing, enterprise operations, and communications networks. By developing technologies that optimize performance, scalability, and efficiency, the group plays a critical role in advancing Intel's leadership in the data center and computing space.

Please consider that this is a temporary position (1 year).

Responsibilities will include but are not limited to:

Architect and design electrical hardware solutions optimized for platform, system, board, and component-level requirements.
Perform schematic capture, PCB layout, and define circuit placement and routing rules for board designs.
Lead power-on, test, and debug activities in the lab to ensure performance and reliability of hardware platforms.

The ideal candidate should show the following behavioral traits:

Strong problem-solving and analytical skills with the willingness to adapt to complex technical challenges.
Effective communication and collaboration capabilities to work within diverse teams.
Good English communication skills.

Qualifications:

Minimum qualifications are required to be initially considered for this position.

Bachelor's degree in Electrical Engineering or related field
2+ years of hands-on experience in hardware analysis and design tools (such as Cadence design suite).
1+ year of experience in technical evaluation processes and testing methodologies.
Intermediate to Advanced English level (Technical literature).

Must have unrestricted, permanent right to work in Mexico (this role is not eligible for visa or immigration sponsorship).

Requirements listed would be obtained through a combination of relevant industry job experience, internship experience, and/or schoolwork/classes/research.

Job Type:

Intel Contract Employee

Shift:

Shift 1 (Mexico)

Primary Location:

Mexico, Guadalajara

Additional Locations:

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

How we rate this

Hardware Design Engineer (Temporary position) at Intel rates 0 out of 100 for how much of the daily work is AI. That makes it Little AI (AI Level 1 of 4). The level is about AI in the job, not seniority.

Classification

Little AI. AI is not part of the work.

●●●● Builds AI80 to 100
●●●○ Works on AI60 to 79
●●○○ Uses AI40 to 59
●○○○ Little AI0 to 39

Levels come from how often the tools, models and workflows of the role are named in the posting itself. Read the description and count the AI tools, models and workflows it names.

Key facts

Hardware Design Engineer (Temporary position) is an open job at Intel.
Level rates this role AI Level 1 of 4: Little AI.
The role is based in Mexico, Guadalajara.
The job was posted on October 13, 2026.
Seniority: mid.
Applications are handled by Intel. Apply on Intel

Prepare for this job

Built from this posting and from similar jobs on Level.

Skills and AI tools this role asks for

Hardware DesignSchematic CapturePcb LayoutCircuit DesignCadence

Questions you could be asked

Tell me about a project where hardware design was part of your work. What did you do?
Tell me about a project where schematic capture was part of your work. What did you do?
Tell me about a project where pcb layout was part of your work. What did you do?
Tell me about a project where circuit design was part of your work. What did you do?
Walk me through how you've used Cadence in your day-to-day work.

Adapt your resume

List these exact terms on your resume: Hardware Design, Schematic Capture, Pcb Layout, Circuit Design, and Cadence. An applicant tracking system matches the wording, not the idea.
Attach one line of real, concrete experience to at least one of them. A tool named with nothing behind it rarely survives a human read.

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