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Intel

Logic Design Engineer

Intel is hiring a Logic Design Engineer. Level rates it ; you can apply on Intel.

Level's read on this job

  • Level rates this role Little AI ●○○○: aI is not part of the work.
  • The posting mentions SystemVerilog, rtl design and logic design among its tools and skills.
  • Level classes it as a mid-level role.
  • Intel has 823 other open roles on Level.
  • Posted in the last few days.

AI in this role

Develop RTL logic designs and integrate high-performance IPs for next-generation client SoCs.

systemverilog
rtl-designlogic-designsoctiming-analysisverification
Job Details:

Job Description:

The Role and Impact :
Join Intel as an SoC Logic Design Engineer, where you will play a pivotal role in developing the logic design for Intel's next-generation Client System-on-Chip (SoC) products. You will contribute to the RTL design, integration of high-performance IPs, and optimization of core functionalities, ensuring world-class technology that powers devices globally. Your work will directly influence product innovation and performance, driving advancements in computing technology.

Business group :
This role is part of the Silicon and Platform Engineering Group (SPE), which focuses on developing cutting-edge semiconductor solutions and delivering world-class silicon products. SPE drives innovation in Client SoCs by integrating advanced IPs and ensuring high-quality functionality to support Intel's mission of creating technology that enriches lives and shapes the future of computing.

Key Responsibilities :

  • Develop RTL designs for internal IPs or integrate high-performance, bandwidth IPs into SoCs.
  • Collaborate with verification teams to ensure functional, feature, and integration validation.
  • Perform quality checks across RTL static analysis, synthesizability assessments, timing/power convergence, netlist quality verification, and functional equivalence validation.
  • Work with design teams and architects to ensure functional integrity, performance, and overall chip quality.
  • Provide innovative solutions for design optimization and contribute to cross-functional reviews.
  • Follow secure development practices to address security threat models and meet design integrity standards.
  • Collaborate with IP providers to integrate and validate IPs at the SoC level, ensuring smooth IP/SoC handoff.

Qualifications:

Minimum Qualifications :

  • Bachelor's degree in Electrical and Electronics Engineering, Computer Engineering, Computer Science, or a related field with 3+ years of hands-on experience in SoC RTL/Logic Design, demonstrated through internships, academic projects, coursework, or hands-on training OR a Master's degree in Electrical and Electronics Engineering, Computer Engineering, Computer Science, or a related field with no prior professional experience.
  • Proficiency in RTL design languages such as SystemVerilog.
  • Basic understanding of digital design concepts, including timing analysis, power optimization, and synthesis techniques.
  • Familiarity with verification methodologies such as OVM/UVM.

Preferred Qualifications :

  • Experience with logic design, integration of high-performance IPs, or pre-silicon validation environments.
  • Knowledge of industry-standard tools for RTL simulation, synthesis, and static timing analysis.
  • Strong problem-solving and communication skills to thrive in a collaborative team environment.

If you're passionate about technology and aspire to contribute to world-changing innovations, we encourage you to take the next step in your career with Intel today.

Job Type:

Experienced Hire

Shift:

Shift 1 (Malaysia)

Primary Location:

Malaysia, Penang

Additional Locations:

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

*

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

How we rate this

Logic Design Engineer at Intel rates 0 out of 100 for how much of the daily work is AI. That makes it Little AI (AI Level 1 of 4). The level is about AI in the job, not seniority.

Classification

Little AI. AI is not part of the work.

  1. ●●●● Builds AI80 to 100
  2. ●●●○ Works on AI60 to 79
  3. ●●○○ Uses AI40 to 59
  4. ●○○○ Little AI0 to 39

Levels come from how often the tools, models and workflows of the role are named in the posting itself. Read the description and count the AI tools, models and workflows it names.

Prepare for this job

Built from this posting and from similar jobs on Level.

Skills and AI tools this role asks for

Rtl DesignLogic DesignSocTiming AnalysisVerificationSystemVerilog

Questions you could be asked

  1. Tell me about a project where rtl design was part of your work. What did you do?
  2. Tell me about a project where logic design was part of your work. What did you do?
  3. Tell me about a project where soc was part of your work. What did you do?
  4. Tell me about a project where timing analysis was part of your work. What did you do?
  5. Tell me about a project where verification was part of your work. What did you do?

Adapt your resume

  • List these exact terms on your resume: Rtl Design, Logic Design, Soc, Timing Analysis, and Verification. An applicant tracking system matches the wording, not the idea.
  • Attach one line of real, concrete experience to at least one of them. A tool named with nothing behind it rarely survives a human read.

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