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NVIDIA

Manager, DFT - Post Silicon

NVIDIA is hiring a Manager, DFT - Post Silicon in Tel Aviv, Israel. Level rates it ; you can apply on NVIDIA.

Level's read on this job

  • On Level's scale, this role is Little AI ●○○○: aI is not part of the work.
  • Tools and skills the posting cites include dft, post silicon validation and ic design.
  • Level classifies it as a mid-level role.
  • Level lists 2,600+ other open roles at NVIDIA.

AI in this role

Manage chip design DFT and post-silicon validation teams to deliver characterization and testing techniques for advanced products.

dftpost-silicon-validationic-designproduct-engineeringtest-engineering

We are looking for a Chip Design DFT/Post Silicon Manager to develop the next generation DFT technologies. As a Chip Design DFT/Post Silicon Manager in the DFT team at NVIDIA, you will lead team that transfer our DFT technologies to post-silicon in various projects and support the enablement. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting Switches, Nic and SoC product lines. We are working closely with a wide range of aspects - chip design, backend, verification and production testing. We are working on the most advanced technologies and complex products. Our DFT solutions are unique, innovative, and we are continuously looking for new and creative solutions to meet the challenging goals.

What you’ll be doing:

Define and develop characterization and validation techniques for post-silicon bring up and production test, spanning electrical, functional, and performance characterization. Working in close coordination with DFT and test engineering, yield, FW and other teams, lead methodology planning for future products and serve as the synchronization point between teams. Day to day, this means:

  • Driving alignment on tooling, flows, and coverage requirements ahead of tape-out and first silicon

  • Translating product requirements and silicon behavior into structured characterization plans with clear coverage targets, risk areas, and Product quality metrics (Test Time , Pattern count and so on).

  • Leading methodology transfer into execution — working with team managers to ensure tooling, methods, and engineers are in place for a smooth handoff

  • Identifying methodology gaps early in the program cycle and resolving them through cross-functional collaboration

What we need to see:

  • B.Sc. in Electrical Engineering (or equivalent experience)

  • 8+ overall years of experience with DFT, IC silicon validation, product engineering, test engineering.

  • 2+ years of managerial experience.

  • Ability to work in a fast-paced, multifaceted work environment with a focus on technical excellence, innovative thinking, and strong analytical skills.

  • Ability to self-manage, show leadership, and possess good social skills.

  • Deep hands-on engineering background — this role leads, but is encouraged to be technically authoritative and roll up sleeves when needed.

  • Strong cross-functional communication skills; comfortable aligning with US-based teams across time zones and organizational boundaries.

Ways to stand out from the crowd:

  • Experience in developing verification environments and random based verification for unit level and system level using verification tools (simulation tools, Verilog, debug tools like Simvision/Debussy/VCS).

  • Experience with Specman/UVM is a plus.

  • Good understanding of RTL design (Verilog).

  • Product Engineering experince.

NVIDIA has some of the most forward-thinking and hardworking people in the world working for us. Are you creative and autonomous? Do you love the challenge of developing the next generation technologies? If so, we want to hear from you. Come, join our DFT verification Team for a challenging and educational environment, where every individual has a significant contribution to our products and achievements!

How we rate this

Manager, DFT - Post Silicon at NVIDIA rates 0 out of 100 for how much of the daily work is AI. That makes it Little AI (AI Level 1 of 4). The level is about AI in the job, not seniority.

Classification

Little AI. AI is not part of the work.

  1. ●●●● Builds AI80 to 100
  2. ●●●○ Works on AI60 to 79
  3. ●●○○ Uses AI40 to 59
  4. ●○○○ Little AI0 to 39

Levels come from how often the tools, models and workflows of the role are named in the posting itself. Read the description and count the AI tools, models and workflows it names.

Prepare for this job

Built from this posting and from similar jobs on Level.

Skills and AI tools this role asks for

DftPost Silicon ValidationIc DesignProduct EngineeringTest Engineering

Questions you could be asked

  1. Tell me about a project where dft was part of your work. What did you do?
  2. Tell me about a project where post silicon validation was part of your work. What did you do?
  3. Tell me about a project where ic design was part of your work. What did you do?
  4. Tell me about a project where product engineering was part of your work. What did you do?
  5. Tell me about a project where test engineering was part of your work. What did you do?

Adapt your resume

  • List these exact terms on your resume: Dft, Post Silicon Validation, Ic Design, Product Engineering, and Test Engineering. An applicant tracking system matches the wording, not the idea.
  • Attach one line of real, concrete experience to at least one of them. A tool named with nothing behind it rarely survives a human read.

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