PDK Engineer

Intel is hiring a PDK Engineer in Bengaluru, India. Level rates it ; you can apply on Intel.

Level's read on this job

On Level's scale, this role is Little AI ●○○○: aI is not part of the work.
Tools and skills the posting cites include Calibre, Icv and Pegasus.
Level classifies it as a mid-level role.
Level lists 842 other open roles at Intel.

AI in this role

Develop, validate, and optimize Design Rule Checking runsets and physical verification flows for advanced semiconductor nodes.

CalibreIcvPegasusVirtuoso

drcsemiconductor-physicsvlsilayout-designautomation

Job Details:

Job Description:

We are looking for a skilled DRC Runset Engineer to develop, validate, support, and optimize Design Rule Checking runsets for advanced semiconductor process technology nodes. The candidate will work closely with process development teams, design rule owners, CAD/EDA teams, and design groups to translate design rules into robust, efficient, and production-quality rule decks.
The role requires strong expertise in DRC rule deck development using industry-standard physical verification tools such as Siemens Calibre, Synopsys ICV, and Cadence Pegasus, along with strong debugging, automation, and problem-solving skills.

Key Responsibilities:

• Develop, maintain, and support DRC runsets/rule decks for advanced semiconductor process nodes.
• Translate process design rules into accurate and efficient physical verification checks.
• Develop and validate complex geometric, connectivity, density, and process-specific design rule checks using tools such as Calibre, ICV, and Pegasus.
• Create comprehensive test cases to validate rule deck functionality, coverage, and correctness.
• Debug DRC rule deck issues and resolve customer/user-reported problems.
• Improve runset quality, runtime efficiency, scalability, and usability.
• Work closely with process developers, design rule owners and develop runsets.
• Design and implement unit-level and end-to-end validation methodologies for DRC runsets and physical verification flows.
• Provide solutions for complex physical verification and design rule implementation challenges.
• Use AI-based tools and automation techniques to improve rule deck development, validation, and debug productivity.
• Support production users and resolve runset-related issues in a timely manner.
• Work in a fast-paced, dynamic environment with strong ownership, creativity, and attention to quality.

Qualifications:

Minimum Qualifications:

• 4+years of experienced Bachelor's or 2+ years of experienced Master's degree in Electronics, VLSI, Computer Engineering, or a related field.
• Strong experience in DRC rule deck/runset development for semiconductor technologies.
• Hands-on expertise with one or more physical verification tools Siemens Calibre, Synopsys ICV, Cadence Pegasus
• Good understanding of semiconductor manufacturing process, layout design rules, and physical verification concepts.
• Experience in writing, debugging, and optimizing DRC checks.
• Hands-on experience with layout and debug tools Cadence Virtuoso, Calibre DRV, IC WorkBench
• Strong programming/scripting skills in languages such as Python, Perl, Tcl, Shell scripting
• Ability to create and maintain validation test cases and regression suites.
• Strong debugging, analytical, and problem-solving skills.

Join us on our mission to shape the future of technology by enabling groundbreaking innovations. If you are passionate about driving excellence in design and automation, we encourage you to apply and help us transform ideas into reality.

Job Type:

Experienced Hire

Shift:

Shift 1 (India)

Primary Location:

India, Bangalore

Additional Locations:

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

How we rate this

PDK Engineer at Intel rates 0 out of 100 for how much of the daily work is AI. That makes it Little AI (AI Level 1 of 4). The level is about AI in the job, not seniority.

Classification

Little AI. AI is not part of the work.

●●●● Builds AI80 to 100
●●●○ Works on AI60 to 79
●●○○ Uses AI40 to 59
●○○○ Little AI0 to 39

Levels come from how often the tools, models and workflows of the role are named in the posting itself. Read the description and count the AI tools, models and workflows it names.

Key facts

PDK Engineer is an open job at Intel.
Level rates this role AI Level 1 of 4: Little AI.
The role is based in India, Bangalore.
The job was posted on August 20, 2026.
Seniority: mid.
Applications are handled by Intel. Apply on Intel

Prepare for this job

Built from this posting and from similar jobs on Level.

Skills and AI tools this role asks for

DrcSemiconductor PhysicsVlsiLayout DesignAutomationCalibreIcvPegasus

Questions you could be asked

Tell me about a project where drc was part of your work. What did you do?
Tell me about a project where semiconductor physics was part of your work. What did you do?
Tell me about a project where vlsi was part of your work. What did you do?
Tell me about a project where layout design was part of your work. What did you do?
Tell me about a project where automation was part of your work. What did you do?

Adapt your resume

List these exact terms on your resume: Drc, Semiconductor Physics, Vlsi, Layout Design, and Automation. An applicant tracking system matches the wording, not the idea.
Attach one line of real, concrete experience to at least one of them. A tool named with nothing behind it rarely survives a human read.

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