Platform Integration Engineer

Intel is hiring a Platform Integration Engineer in Santa Clara, United States. It pays $164k-$232k a year and Level rates it ; you can apply on Intel.

Level's read on this job

On Level's scale, this role is Little AI ●○○○: aI is not part of the work.
The posting mentions SystemVerilog, rtl design and logic design among its tools and skills.
Level classes it as a senior role.
Intel has 798 other open roles on Level.
Posted within the past two weeks.

AI in this role

Design and validate logic for semiconductor IP blocks using SystemVerilog and front-end tools.

systemverilog

rtl-designlogic-designsynthesisstatic-timing-analysis

Job Details:

Job Description:

About Central Engineering Group

The Central Engineering Group (CEG) is Intel's hub for driving innovation and excellence in silicon development. Focused on engineering solutions that power Intel's flagship products, CEG architects, designs, and validates IP foundational to Intel's broader technology portfolio. By joining this team, you will be part of a collaborative, inclusive environment driving advancements to strengthen Intel's leadership in the semiconductor industry.

Position Overview

As an IP Logic Design Engineer at Intel, you will play a pivotal role in developing high-quality IP blocks and subsystems for integration into full chip designs. You'll be responsible for creating cutting-edge logic designs, optimizing power, performance, and area, and ensuring seamless integration with the broader system. Your contributions will directly impact Intel's ability to deliver next-generation silicon solutions with speed, efficiency, and reliability.

Key Responsibilities

• Develop logic designs, register transfer level (RTL) coding, and simulation for IP blocks and subsystems for integration into full chip designs

• Define architecture and microarchitecture features and ensure their implementation in the design

• Optimize design logic to meet power, performance, area, and timing goals while maintaining physical implementation integrity

• Review verification plans and address RTL test failures to ensure accurate validation of design features

• Collaborate with physical design teams to address floorplan limitations and integrate designs seamlessly

• Drive quality assurance compliance to enable smooth IP-to-SoC handoff

What We're Looking For

To be successful in this role, you should demonstrate the following professional traits:

• Ability to collaborate effectively across cross-functional and geographically distributed teams • Strong attention to detail when reviewing verification plans and resolving design failures • A passion for innovation and continuous improvement in a fast-paced engineering environment

Qualifications:

Minimum Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related STEM field with 6+ years of experience with RTL design and SystemVerilog OR Master's degree in relevant field with 4+ years of experience with RTL design and SystemVerilog

The experience must include:

• Industry-standard tools for front-end design, including synthesis, static timing analysis (STA), and lint checks

• AMBA protocols and coherent protocols such as IDI or CHI

• Hardware design concepts such as logic design, state machines, and network-on-chip architectures

Preferred Qualifications

• Experience with high-speed interconnect designs and power-performance optimization

• Proficiency in programming languages such as Python, Perl, or Tcl for scripting automation

• Demonstrated ability to collaborate effectively with cross-functional teams and geographically distributed groups

We invite you to bring your expertise and passion to Intel, where you'll work alongside the brightest minds in the industry to develop innovative technologies that redefine the future of computing. Apply now to embark on a rewarding journey and make a lasting impact.

Job Type:

Experienced Hire

Shift:

Shift 1 (United States of America)

Primary Location:

US, California, Santa Clara

Additional Locations:

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $164,470.00-232,190.00 USD

The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

How we rate this

Platform Integration Engineer at Intel rates 0 out of 100 for how much of the daily work is AI. That makes it Little AI (AI Level 1 of 4). The level is about AI in the job, not seniority.

Classification

Little AI. AI is not part of the work.

●●●● Builds AI80 to 100
●●●○ Works on AI60 to 79
●●○○ Uses AI40 to 59
●○○○ Little AI0 to 39

Levels come from how often the tools, models and workflows of the role are named in the posting itself. Read the description and count the AI tools, models and workflows it names.

Key facts

Platform Integration Engineer is an open job at Intel.
Level rates this role AI Level 1 of 4: Little AI.
The listed salary is $164k-$232k a year.
The role is based in US, California, Santa Clara.
The job was posted on October 21, 2026.
Seniority: senior.
Applications are handled by Intel. Apply on Intel

Prepare for this job

Built from this posting and from similar jobs on Level.

Skills and AI tools this role asks for

Rtl DesignLogic DesignSynthesisStatic Timing AnalysisSystemVerilog

Questions you could be asked

Tell me about a project where rtl design was part of your work. What did you do?
Tell me about a project where logic design was part of your work. What did you do?
Tell me about a project where synthesis was part of your work. What did you do?
Tell me about a project where static timing analysis was part of your work. What did you do?
Walk me through how you've used SystemVerilog in your day-to-day work.

Adapt your resume

List these exact terms on your resume: Rtl Design, Logic Design, Synthesis, Static Timing Analysis, and SystemVerilog. An applicant tracking system matches the wording, not the idea.
Attach one line of real, concrete experience to at least one of them. A tool named with nothing behind it rarely survives a human read.

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