Senior ASIC Design Engineer

NVIDIA is hiring a Senior ASIC Design Engineer in Santa Clara, United States. It pays $168k-$265k a year and Level rates it ; you can apply on NVIDIA.

Level's read on this job

Level rates this role Little AI ●○○○: aI is not part of the work.
Tools and skills the posting cites include Verilog, Python and Perl.
Level classifies it as a senior role.
Level lists 2,700+ other open roles at NVIDIA.

AI in this role

Design and implement complex SoC and GPU architectures for graphics, autonomous vehicles, and accelerated computing.

verilogpythonperlc

asic-designrtlmicro-architecturevlsilogic-synthesis

NVIDIA is seeking best-in-class ASIC Design Engineers to design and implement the world’s leading SoC's and GPU's. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of exceptional people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing.

What you’ll be doing:

As a key member of the Design team, you will be responsible for the implementation of GPU sub-system modules.
Make architectural trade-offs based on features, performance requirements and system limitations.
You are expected to own micro-architecture, implement RTL, and deliver a fully verified, synthesis/timing clean design.
Support post-silicon validation activities.
Work with architects, other designers, pre- and post-silicon verification teams, synthesis, timing and back-end teams to accomplish your tasks.

What we need to see:

Masters Degree (or equivalent experience) in Electrical Engineering or Computer Engineering.
8+ years of proven experience working on ASIC design and development.
Experience in micro-architecture and RTL development of complex designs in Verilog.
Exposure to Digital systems and VLSI design, Computer Architecture, Computer Arithmetic, CMOS transistors and circuits is required.
Understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, bring-up & lab debug.
Prior experience with arbiters, scheduling, synchronization & bus protocols, interconnect networks, and/or caches is desirable.

Ways to stand out from the crowd:

Knowledge of PCI-Express (Gen 3 and above) or CXL protocol is very helpful; your firsthand design experience on it is a big plus.
Python, Perl and C/C++ programming language experience desirable.
Good debugging and analytical skills.
Strong interpersonal skills and ability & desire to work as a great teammate.

NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us. Are you creative and autonomous? Do you love the challenge of crafting the fastest and most power efficient chips in their class? If so, we want to hear from you.

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 168,000 USD - 264,500 USD for Level 4, and 196,000 USD - 310,500 USD for Level 5.

You will also be eligible for equity and benefits.

Applications for this job will be accepted at least until October 9, 2026.

This posting is for an existing vacancy.

NVIDIA uses AI tools in its recruiting processes.

NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.

How we rate this

Senior ASIC Design Engineer at NVIDIA rates 10 out of 100 for how much of the daily work is AI. That makes it Little AI (AI Level 1 of 4). The level is about AI in the job, not seniority.

Classification

Little AI. AI is not part of the work.

●●●● Builds AI80 to 100
●●●○ Works on AI60 to 79
●●○○ Uses AI40 to 59
●○○○ Little AI0 to 39

Levels come from how often the tools, models and workflows of the role are named in the posting itself. Read the description and count the AI tools, models and workflows it names.

Key facts

Senior ASIC Design Engineer is an open job at NVIDIA.
Level rates this role AI Level 1 of 4: Little AI.
The listed salary is $168k-$265k a year.
The role is based in US, CA, Santa Clara.
The job was posted on October 5, 2026.
Seniority: senior.
Applications are handled by NVIDIA. Apply on NVIDIA

Prepare for this job

Built from this posting and from similar jobs on Level.

Skills and AI tools this role asks for

Asic DesignRtlMicro ArchitectureVlsiLogic SynthesisVerilogPythonPerl

Questions you could be asked

Tell me about a project where asic design was part of your work. What did you do?
Tell me about a project where rtl was part of your work. What did you do?
Tell me about a project where micro architecture was part of your work. What did you do?
Tell me about a project where vlsi was part of your work. What did you do?
Tell me about a project where logic synthesis was part of your work. What did you do?

Adapt your resume

List these exact terms on your resume: Asic Design, Rtl, Micro Architecture, Vlsi, and Logic Synthesis. An applicant tracking system matches the wording, not the idea.
Attach one line of real, concrete experience to at least one of them. A tool named with nothing behind it rarely survives a human read.

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