Level

Cerebras

Senior ASIC RTL Design Engineer, AI Hardware

AI in this role

Design and develop next-generation AI hardware and wafer-scale chips as a senior ASIC RTL design engineer.

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ai-researchrtl-designasichardware-accelerationai-chipsmicro-architecture

Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. This architecture allows Cerebras to deliver industry-leading training and inference speeds; over 10 times faster than GPU-based hyperscale cloud inference services.

This order of magnitude increase in speed is transforming the user experience of AI applications, unlocking real-time iteration and increasing intelligence via additional agentic computation.

Cerebras works with the leading model labs, global enterprises, and cutting-edge AI-native startups. OpenAI recently announced a multi-year partnership with Cerebras, to deploy 750 megawatts of scale, transforming key workloads with ultra high-speed inference.

About The Role:

As a senior front-end design engineer, you will be a key part of the world-class team designing and developing the next generations of the Cerebras Wafer Scale Engine (WSE). This role requires deep expertise in RTL design and integration, with a strong focus on delivering high-performance, power-efficient, and scalable solutions. You will collaborate closely with the design verification, physical design, software and system teams to bring innovative semiconductor architectures from concept to production, addressing the unique challenges of building WSE systems.

 

Responsibilities:

  • Drive all aspects of chip design, including Functional Specification, Micro-architecture, RTL development, Synthesis.

  • Work closely with PD team members for design closure to meet PPA goals.

  • Work closely with Design verification and DFT teams for achieving the best functional and test coverage.

  • Work with software and system teams to understand opportunities to deliver optimal performance and feature set for the product.

  • Debug silicon-level functional, timing, and power issues during bring up.

  • Requirements

  • Master’s degree in Computer Science, Electrical Engineering, or equivalent.

  • Can work in a hybrid work environment.

  • 8+ years of experience in delivering complex, high performance high quality RTL designs.

  • Experience with Front End Chip integration and third-party IP integration.

  • Demonstrated experience in high-performance computing, GPU/CPU designs, machine learning or related fields.

  • Proven track record of multiple silicon success.

  • Experience collaborating with external vendors.

  • Networking stack experience including TCP/IP, RDMA and Ethernet.

  • Knowledge of PCIe, CPU interfaces and Serdes technology.

  • Working knowledge of scripting tools : Python, TCL.

 

Assets:

  • Experience with FPGA development toolchain, including Place and Route, Floor planning and Timing Analysis is a plus.

  • Experience managing external ASIC vendor through product development cycle.

 

Location: Sunnyvale, CA (Open to Remote)

 

The base salary range for this position is $200,000 to $290,000 annually. Actual compensation may include bonus and equity, and will be determined based on factors such as experience, skills, and qualifications.

Why Join Cerebras

People who are serious about software make their own hardware. At Cerebras, we have built a breakthrough architecture that is unlocking new opportunities for the AI industry. With dozens of model releases and rapid growth, we’ve reached an inflection point in our business. Members of our team tell us there are five main reasons they joined Cerebras:

  1. Build a breakthrough AI platform beyond the constraints of the GPU.

  2. Publish and open source their cutting-edge AI research.

  3. Work on one of the fastest AI supercomputers in the world.

  4. Enjoy job stability with startup vitality.

  5. Our simple, non-corporate work culture that respects individual beliefs.

Find out more about what it's like to work at Cerebras here!

Apply today and become part of the forefront of groundbreaking advancements in AI!

Cerebras Systems is committed to creating an equal and diverse environment and is proud to be an equal opportunity employer. We celebrate different backgrounds, perspectives, and skills. We believe inclusive teams build better products and companies. We try every day to build a work environment that empowers people to do their best work through continuous learning, growth and support of those around them.

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How we score this

Senior ASIC RTL Design Engineer, AI Hardware at Cerebras scores 90 out of 100 on AI centrality, which makes it AI Level 4 of 4 (Builds AI) on this board. The level measures how much of the work is AI, not seniority.

Classification

AI Level 4. Building AI systems is the job itself: without AI, the role would not exist.

  1. AI Level 480 to 100
  2. AI Level 360 to 79
  3. AI Level 240 to 59
  4. AI Level 10 to 39

Bands come from how often the tools, models and workflows of the role are named in the posting itself. Open the description and count.

Prepare for this job

A free preview built only from this posting: what it asks for, what you could be asked in an interview, and how to adjust your resume.

Skills and AI tools this role asks for

AI ResearchRtl DesignAsicHardware AccelerationAI ChipsMicro ArchitectureOpenAIPython

Questions you could be asked

  1. Tell me about a research question you investigated. What did you find?
  2. Tell me about a project where rtl design was part of your work. What did you do?
  3. Tell me about a project where asic was part of your work. What did you do?
  4. Tell me about a project where hardware acceleration was part of your work. What did you do?
  5. Tell me about a project where ai chips was part of your work. What did you do?

Adapt your resume

  • List these exact terms on your resume: AI Research, Rtl Design, Asic, Hardware Acceleration, and AI Chips. An applicant tracking system matches the wording, not the idea.
  • Attach one line of real, concrete experience to at least one of them — a tool named with nothing behind it rarely survives a human read.
  • Lead with what you built, trained or shipped — this role is judged on the AI system itself, not the tools around it.

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