Senior CPU Architecture and Benchmarking Engineer

Intel is hiring a Senior CPU Architecture and Benchmarking Engineer. It pays $191k-$269k a year and Level rates it ; you can apply on Intel.

Level's read on this job

Little AI ●○○○ is how Level rates this role: aI is not part of the work.
Tools and skills the posting cites include microbenchmarking, cpu architecture and performance simulation.
Level classifies it as a senior role.
Level lists 823 other open roles at Intel.

AI in this role

Drive low-level investigations into CPU designs, crafting microbenchmarks to guide future processor architecture.

microbenchmarkingcpu-architectureperformance-simulationrtlmicroarchitecture

Job Details:

Job Description:

About the Role

Join Intel's architecture team as a Senior CPU Architecture and Benchmarking Engineer. You will drive rigorous, low-level investigations into CPU designs, crafting targeted microbenchmarks that expose microarchitectural behavior at fine granularity and translating those findings into actionable architectural guidance. Your work will bridge the gap between silicon measurement, software behavior, and architectural definition, playing a key role in shaping Intel's future CPU roadmap.

Key Responsibilities

Design, implement, and analyze pinpointed microbenchmarks to explore and characterize low-level microarchitectural behavior including branch prediction, instruction fetch/decode, execution units, memory subsystem, prefetchers, and power delivery interactions
Investigate and document microarchitectural details of CPU designs through systematic benchmarking and analysis
Evaluate the impact of system software layers — including OS schedulers, runtime libraries, compilers, and firmware — on end-product CPU performance and power efficiency
Identify power/performance gaps and propose concrete architectural solutions and mitigations
Collaborate with silicon lab, simulation, backend, and RTL teams to correlate benchmarking findings with pre-silicon models and post-silicon measurements
Explore and evaluate proposed microarchitectural ideas in CPU performance simulators, providing quantitative measure of value
Develop and maintain tooling, test infrastructure, and analysis frameworks to support repeatable and scalable benchmarking workflows
Communicate technical findings clearly and persuasively in written reports and presentations to senior engineering and product teams

To Be Successful in This Role, You Should Demonstrate

Intellectual curiosity and a systematic mindset when investigating complex microarchitectural behavior, with the rigor to design experiments that yield clear, reproducible conclusions
Strong cross-functional collaboration skills, with the ability to work effectively across silicon, simulation, and software teams to align findings and drive architectural decisions
The ability to communicate complex technical findings with clarity and confidence to both engineering peers and senior leadership audiences

Qualifications:

Minimum Qualifications

Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or a related discipline with 8+ years of relevant industry experience, OR a Master's Degree in a related discipline with 6+ years of relevant industry experience
Deep understanding of out-of-order CPU microarchitecture, including pipeline stages, execution resources, memory hierarchy, and power/performance interactions
Demonstrated experience designing and interpreting low-level microbenchmarks for CPU characterization
Proficiency in assembly programming and low-level performance tooling (e.g., EMON/PMU counters, VTune, or equivalent)
Strong background in performance analysis methodologies, bottleneck identification, and quantitative trade-off evaluation
Proficiency in C/C++ and scripting languages (Python or similar) for benchmark development and data analysis

Preferred Qualifications

Familiarity with cycle-accurate CPU performance simulators and the ability to model and evaluate new microarchitectural features
Understanding of software stack impacts on CPU performance, including OS scheduler behavior, memory allocators, compiler code generation, and BIOS/firmware tuning
Experience reading or debugging RTL to investigate microarchitectural behavior or validate benchmark hypotheses
Track record of translating benchmarking insights into concrete architectural recommendations or published technical contributions

Job Type:

Experienced Hire

Shift:

Shift 1 (United States of America)

Primary Location:

US, Oregon, Hillsboro

Additional Locations:

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $190,610.00-269,100.00 USD

The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

How we rate this

Senior CPU Architecture and Benchmarking Engineer at Intel rates 0 out of 100 for how much of the daily work is AI. That makes it Little AI (AI Level 1 of 4). The level is about AI in the job, not seniority.

Classification

Little AI. AI is not part of the work.

●●●● Builds AI80 to 100
●●●○ Works on AI60 to 79
●●○○ Uses AI40 to 59
●○○○ Little AI0 to 39

Levels come from how often the tools, models and workflows of the role are named in the posting itself. Read the description and count the AI tools, models and workflows it names.

Key facts

Senior CPU Architecture and Benchmarking Engineer is an open job at Intel.
Level rates this role AI Level 1 of 4: Little AI.
The listed salary is $191k-$269k a year.
The role is based in US, Oregon, Hillsboro.
The job was posted on October 2, 2026.
Seniority: senior.
Applications are handled by Intel. Apply on Intel

Prepare for this job

Built from this posting and from similar jobs on Level.

Skills and AI tools this role asks for

MicrobenchmarkingCpu ArchitecturePerformance SimulationRtlMicroarchitecture

Questions you could be asked

Tell me about a project where microbenchmarking was part of your work. What did you do?
Tell me about a project where cpu architecture was part of your work. What did you do?
Tell me about a project where performance simulation was part of your work. What did you do?
Tell me about a project where rtl was part of your work. What did you do?
Tell me about a project where microarchitecture was part of your work. What did you do?

Adapt your resume

List these exact terms on your resume: Microbenchmarking, Cpu Architecture, Performance Simulation, Rtl, and Microarchitecture. An applicant tracking system matches the wording, not the idea.
Attach one line of real, concrete experience to at least one of them. A tool named with nothing behind it rarely survives a human read.

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