Senior Design Verification Engineer

Cisco is hiring a Senior Design Verification Engineer in Belgrade, Serbia. Level rates it ; you can apply on Cisco.

Level's read on this job

Level rates this role Little AI ●○○○: aI is not part of the work.
Tools and skills the posting cites include SystemVerilog, UVM and Pcie.
Level classifies it as a senior role.
Level lists 1,400+ other open roles at Cisco.

AI in this role

Implement functional verification infrastructure for high-performance networking ASICs using SystemVerilog and UVM.

SystemVerilogUVMPcieSpiI2cJtag

asic-verificationdigital-logicdebuggingscripting

Meet the Team

Join our SiliconOne team in Serbia, specializing in ASIC functional verification for Cisco Silicon One chips—high-performance networking chips utilized by major data centers worldwide. Collaborate with us on functional verification using SystemVerilog/UVM, and take advantage of opportunities to engage in various development stages, from architectural discussions to emulation and simulation support. Collaborate with global teams, design and block owners, chiplet and full-chip owners as well as emulation, compiler, and software development teams. Our team blends experienced and energetic engineers, fostering collaboration and transparency in an environment built on trust.

Your Impact

Implementation of DV infrastructure for block, cluster, and TOP-level environments.
Maintaining existing DV environments and enhancing them.
Ensuring complete verification coverage through implementation and review of code and functional coverage.
Working closely with architects and designers to ensure verification completeness.
Supporting tests done with emulation.
Engage in tasks to prepare for post-silicon-validation.

Minimum Requirements:

5+ years’ experience in digital logic design verification
Advanced knowledge of SystemVerilog and UVM
Advanced debug skills pre-silicon and in-lab

Preferred Requirements:

Scripting abilities
System integration knowledge (AMBA, PCIe. SPI, I2C, JTAG, CPU)
Basic SW knowledge (chop driver level)
Basic design knowledge

Why Cisco?

At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.

Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.

We are Cisco, and our power starts with you.

How we rate this

Senior Design Verification Engineer at Cisco rates 10 out of 100 for how much of the daily work is AI. That makes it Little AI (AI Level 1 of 4). The level is about AI in the job, not seniority.

Classification

Little AI. AI is not part of the work.

●●●● Builds AI80 to 100
●●●○ Works on AI60 to 79
●●○○ Uses AI40 to 59
●○○○ Little AI0 to 39

Levels come from how often the tools, models and workflows of the role are named in the posting itself. Read the description and count the AI tools, models and workflows it names.

Key facts

Senior Design Verification Engineer is an open job at Cisco.
Level rates this role AI Level 1 of 4: Little AI.
The role is based in Belgrade, Serbia.
The job was posted on August 4, 2026.
Seniority: senior.
Applications are handled by Cisco. Apply on Cisco

Prepare for this job

Built from this posting and from similar jobs on Level.

Skills and AI tools this role asks for

Asic VerificationDigital LogicDebuggingScriptingSystemVerilogUVMPcieSpi

Questions you could be asked

Tell me about a project where asic verification was part of your work. What did you do?
Tell me about a project where digital logic was part of your work. What did you do?
Tell me about a project where debugging was part of your work. What did you do?
Tell me about a project where scripting was part of your work. What did you do?
Walk me through how you've used SystemVerilog in your day-to-day work.

Adapt your resume

List these exact terms on your resume: Asic Verification, Digital Logic, Debugging, Scripting, and SystemVerilog. An applicant tracking system matches the wording, not the idea.
Attach one line of real, concrete experience to at least one of them. A tool named with nothing behind it rarely survives a human read.

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