SoC Compute/Memory Subsystem Architect

Job Description:

About the Role

The CEG NAG (Networking Architecture Group) is Intel's premier team focused on defining the future of high-performance networking silicon. Our team architects next-generation networking solutions that enable hyperscale data centers, cloud infrastructure, and AI workloads to achieve unprecedented performance and efficiency. We specialize in IPU/DPU platforms, advanced packet processing architectures, and programmable networking technologies that form the backbone of modern distributed computing systems.

We are seeking a Senior SoC Compute & Memory Architect to define and drive the architecture of compute complexes and high-performance memory subsystems for next-generation IPU/DPU platforms.

This role is responsible for end-to-end architecture of CPU clusters, cache hierarchies, coherency models, and memory subsystems. You will optimize system-level performance, scalability, power efficiency, and programmability while ensuring seamless interaction with networking, storage, and accelerator subsystems in hyperscale environments.

What You’ll Do

Key responsibilities will include but not limited to:

Cache Hierarchy and Coherency Architecture
1. Define and evolve multi-level cache hierarchy (private/shared caches, system-level cache).
2. Architect coherency models across compute cores, accelerators, and IO subsystems (coherent vs non-coherent interactions).
3. Evaluate tradeoffs between latency, bandwidth, scalability, and coherence domain complexity.

Memory Subsystem Architecture
1. Architect system memory subsystems including:
-DDR / LPDDR interfaces.
-Memory controllers and scheduling policies.
-Bandwidth provisioning and scaling strategies.
2. Work with Performance architect in define memory access models for compute, network, and accelerator subsystems.
3. Ensure optimal balance between latency-sensitive control workloads and bandwidth-intensive datapath workloads.

IO Memory and Virtualization Architecture (SMMU/IOMMU)
1. Define architecture for SMMU/IOMMU supporting virtualization-heavy IPU workloads.
2. Architect features such as:
-Multi-tenant isolation and security boundaries.
-Shared vs isolated memory models.
3. Ensure efficient interaction between host, IPU/DPU compute, and offload engines.

System-Level Integration (Compute Network Storage)
1. Architect integration between:
-Compute subsystem.
-Network subsystem (packet processing pipelines).
-Storage and accelerator subsystems.
2. Optimize data movement across subsystems to minimize copies, latency, and bandwidth overhead.
3. Drive system architecture decisions for balanced SoC performance.

Power, Efficiency, and Scaling Strategy
1. Define compute and memory strategies for power efficiency and DVFS scalability.
2. Architect mechanisms for:
-Memory bandwidth throttling / prioritization.
-Per-subsystem scaling.
3. Optimize performance-per-watt at system level.

Multi-Generation Architecture Roadmap
1. Lead long-term roadmap for compute and memory evolution across IPU/DPU product generations.
2. Define scaling strategies for:
-Core count and frequency.
-Memory bandwidth and capacity.
-Cache scaling and topology.
3. Ensure backward compatibility and smooth migration across product lines.

Cross-Functional Leadership
1. Collaborate with teams across:
-Networking subsystem (NSS).
-SoC fabric/interconnect.
-Firmware, OS, and drivers.
-Validation and performance modeling and testing.
2. Drive architecture alignment and resolve cross-domain tradeoff.

Behavioral traits that we are looking for: (soft skills that you would like to see in a candidate)

• Architectural vision: Defines long-term strategy across system domains.
• Influence without authority: Drives alignment across multiple teams and disciplines.
• Systems thinking: Understands interactions across compute, memory, network, and software.
• Decision-making under ambiguity: Makes sound tradeoffs with incomplete data.
• Collaboration: Builds strong cross-functional relationships.
• Customer-oriented mindset: Translates workload needs into architectural innovations.
• Ownership and accountability: Drives initiatives end-to-end.
• Continuous learning: Stays current with evolving compute and memory technologies.

Intel invests in our people and offers a complete and competitive package of benefits employees and their families through every stage of life.

See Intel Benefits for more details.

Qualifications:

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications
Batchelor's degree in Electrical Engineering, Computer Engineering, or in a STEM related Field of Study.

You must have 10 + years of experience in the following:

• SoC / CPU / memory subsystem architecture.
• CPU architecture and cache hierarchies.
• Memory subsystems (DDR/HBM, controllers, QoS).
• Coherent/Non-Coherent interconnect architectures.
• Experience in system-level performance and PPA tradeoff analysis.
• Drive architecture definition from concept to silicon.

Preferred Qualifications:

• Post Graduate degree in Electrical Engineering, Computer Engineering, or in a STEM related Field of Study.
• ARM and x86 compute and memory subsystem experience, including NUMA systems, cache coherency, or large scale platform architectures.
• Experience with IPU / SmartNIC or accelerator centric SoCs, particularly in cloud and hyperscale environments.
• Familiarity with PCIe, CXL, and memory semantics for high performance IO.
• Track record of multi generation architectural ownership and mentoring other architects.

Join us in building a brighter future through technology innovation!

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Posting Statement:

Position of Trust

EU Salary

We offer a total compensation package that ranks among the best in the industry.

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