SoC Validation Engineer – Power Management

Intel is hiring a SoC Validation Engineer – Power Management. It pays $164k-$269k a year and Level rates it ; you can apply on Intel.

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Job Details:

Job Description:

The world is transforming - and so is Intel. Intel is a company of bold and curious inventors and problem solvers who create some of the most astounding technology advancements and experiences in the world. With a legacy of relentless innovation and a commitment to bring smart, connected devices to every person on Earth, our diverse and brilliant teams are continually searching for tomorrow's technology and revel in the challenge that changing the world for the better brings. We work every single day to design and manufacture silicon products that empower people's digital lives. Come join us and do something wonderful.

The Role and Impact:
Intel is seeking a motivated and experienced SoC Validation Engineer to join our Power Management Validation team. In this role, you will be responsible for validating power management architectures and features that enable Intel's next-generation products. You will play a critical role in ensuring design quality, functionality, and power efficiency by developing innovative validation strategies, executing comprehensive test plans, and driving debug activities across complex SoC designs.

As a SoC Power Management Validation Engineer, you will work closely with architecture, design, and verification teams to validate key power management features including Dynamic Voltage and Frequency Scaling (DVFS), power gating, clock gating, reset flows, low-power states, thermal management, and telemetry. You will contribute to the development of advanced validation environments, uncover design issues early in the development cycle, and drive solutions that improve product quality and readiness. This position offers an opportunity to influence future Intel products while expanding your technical leadership and validation expertise.

Business group:
You will be joining Intel's Data Center Group (DCG), a global leader in designing and delivering cutting-edge technologies that drive data center innovation and transformation. The group specializes in developing high-performance solutions to accelerate computing, storage, and networking capabilities, supporting Intel's mission to power the world's digital infrastructure.

Key Responsibilities:
- Develop and execute comprehensive validation plans to ensure power management features meet architectural and functional specifications.
- Design, develop, and maintain validation environments, automated test content, and debug infrastructure for power management validation.
- Validate critical power management features including: Dynamic Voltage and Frequency Scaling (DVFS), Power Gating and Clock Gating, Low-Power States and Power State Transitions, Reset and Power Sequencing, Thermal Management Features, Telemetry and Monitoring Logic.
- Develop validation content and infrastructure using industry-standard methodologies and tools such as SystemVerilog, UVM, simulation, and emulation platforms.
- Execute simulation and emulation workloads to validate design functionality and identify issues early in the product development cycle.
- Analyze validation results, coverage metrics, and performance data to improve design quality and validation effectiveness.
- Drive root cause analysis, debug, and resolution of complex design issues in collaboration with architecture, RTL design, and verification teams.
- Develop and maintain automation frameworks, regression environments, dashboards, and data analysis tools to improve validation efficiency and coverage.
- Review architecture specifications and design changes to assess validation impact and ensure comprehensive feature coverage.
- Contribute to validation methodology improvements and best practices across multiple product generations.
- Mentor junior engineers and provide technical leadership on complex validation and debug challenges.
- Continuously explore new technologies, automation techniques, and AI-assisted solutions to improve execution and outcomes.

Qualifications:

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your degree, research and or relevant previous job and or internship experiences.

Minimum Qualifications:
- Bachelors & 6+ years or Masters & 4+ years or PhD & 2+ years degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.

- 10+ years of experience in pre-silicon validation, functional validation, design verification, or silicon validation.

- Strong understanding of digital design fundamentals, computer architecture, and SoC design concepts.

- Strong knowledge of SystemVerilog and UVM-based validation methodologies.

- Experience with simulation or emulation environments, debugging and root-cause analysis skills.

- Knowledge in Python or Perl or Shell, or similar scripting languages.

Preferred Qualifications:
- Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.

- Experience validating power management architecture and features in complex SoC designs, such as: Dynamic Voltage and Frequency Scaling (DVFS), Power Gating, Clock Gating, Low-Power State Management, Reset and Power Sequencing, Thermal Management Features.

- Experience developing validation plans, test content, and coverage-driven validation strategies.

- Experience in one or more of the following areas: Functional Validation, Design Verification, Coverage-Driven Verification, Emulation-Based Validation, Low-Power Verification Methodologies, Reset Validation, Power State Validation, Telemetry Feature Validation.

- Familiarity with assertion-based verification, formal verification, and advanced validation automation techniques.

- Demonstrated ability to lead technical initiatives and mentor engineers.

- Strong collaboration skills and ability to work effectively across architecture, design, and validation teams.

- Experience leveraging AI and advanced analytics to improve validation productivity and quality.

- Passion for innovation, continuous improvement, and technical excellence.

- Excellent analytical, problem-solving, and communication skills.

Your expertise and enthusiasm for cutting-edge technology will make a tangible difference in shaping the future of data center innovation. Join us and be part of a team that drives meaningful change and delivers world-class solutions to customers across the globe.

Job Type:

Experienced Hire

Shift:

Shift 1 (United States of America)

Primary Location:

US, California, Folsom

Additional Locations:

US, California, Santa Clara, US, Oregon, Hillsboro

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $164,470.00-269,100.00 USD

The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

How we rate this

SoC Validation Engineer – Power Management at Intel rates 30 out of 100 for how much of the daily work is AI. That makes it Little AI (AI Level 1 of 4). The level is about AI in the job, not seniority.

Classification

Little AI. AI is not part of the work.

●●●● Builds AI80 to 100
●●●○ Works on AI60 to 79
●●○○ Uses AI40 to 59
●○○○ Little AI0 to 39

Levels come from how often the tools, models and workflows of the role are named in the posting itself. Read the description and count the AI tools, models and workflows it names.