Staff SOC DFT Engineer

Intel is hiring a Staff SOC DFT Engineer. Level rates it ; you can apply on Intel.

Level's read on this job

Level rates this role Little AI ●○○○: aI is not part of the work.
The posting mentions Verilog, Vhdl and SystemVerilog among its tools and skills.
Level classes it as a senior role.
Intel has 805 other open roles on Level.

AI in this role

Develop advanced DFT methodologies, optimize workflows with AI, and enhance testability for complex SoC designs.

verilogvhdlsystemverilogsynopsys-dft-compilermentor-tessentcadence-moduspython

dftsoc-designrtl-designtestabilitydebugging

Job Details:

Job Description:

The Role and Impact
Are you ready to make a significant contribution to cutting-edge semiconductor designs? As a DFT Design Engineer, you will play a critical role in shaping the testability, debuggability and reliability of complex SoC (System-on-Chip) designs. You will work closely with cross-functional teams, influencing designs from concept to production, and ensuring our products meet the highest quality standards. In this role, you will develop innovative DFT/DFD methodologies, optimize workflow with AI, and enhance post silicon efficiency. Your work will directly impact Intel's ability to deliver world-class semiconductor solutions that advance technology across industries.

Key Responsibilities :

Develop and implement advanced DFT methodologies for complex SoC designs to maximize test coverage and efficiency.
Collaborate with design, verification, and manufacturing teams to define and optimize post silicon strategies and requirements.
Integrate DFT/DFD features into RTL and ensure verification of design for testability requirements.
Collaborate with post-silicon teams to debug and validate DFT features.
Stay current with emerging trends, AI adoption and technologies in DFT/DFD to ensure best practices are incorporated into workflows.

Qualifications:

Minimum Qualifications :

Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field.
5+ years of experience in DFT, SoC design, or related semiconductor design areas.
Expertise in RTL design using hardware description languages like Verilog, VHDL, or SystemVerilog.

Preferred Qualifications :

Familiar with AI application.
Familiarity with advanced DFT methods for low-power or high-performance SoC designs.
Understanding of industry standards such as IEEE 1687 (IJTAG), 1149.1 (JTAG), or IEEE 1500 (Core Test).
Advanced knowledge of industry-standard DFT tools such as Synopsys DFT Compiler, Mentor Tessent, or Cadence Modus.
Knowledge of Python or other scripting languages for design automation.
Hands-on experience with managing multi-functional teams or complex SoC projects.

We are looking for a visionary DFT engineer who thrives in a collaborative and innovative environment, and who is excited by the opportunity to contribute to groundbreaking technology. Join us to shape the future of computing and leave your mark on the world.

Job Type:

Experienced Hire

Shift:

Shift 1 (Malaysia)

Primary Location:

Malaysia, Penang

Additional Locations:

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

How we rate this

Staff SOC DFT Engineer at Intel rates 20 out of 100 for how much of the daily work is AI. That makes it Little AI (AI Level 1 of 4). The level is about AI in the job, not seniority.

Classification

Little AI. AI is not part of the work.

●●●● Builds AI80 to 100
●●●○ Works on AI60 to 79
●●○○ Uses AI40 to 59
●○○○ Little AI0 to 39

Levels come from how often the tools, models and workflows of the role are named in the posting itself. Read the description and count the AI tools, models and workflows it names.

Key facts

Staff SOC DFT Engineer is an open job at Intel.
Level rates this role AI Level 1 of 4: Little AI.
The role is based in Malaysia, Penang.
The job was posted on September 21, 2026.
Seniority: senior.
Applications are handled by Intel. Apply on Intel

Prepare for this job

Built from this posting and from similar jobs on Level.

Skills and AI tools this role asks for

DftSoc DesignRtl DesignTestabilityDebuggingVerilogVhdlSystemVerilog

Questions you could be asked

Tell me about a project where dft was part of your work. What did you do?
Tell me about a project where soc design was part of your work. What did you do?
Tell me about a project where rtl design was part of your work. What did you do?
Tell me about a project where testability was part of your work. What did you do?
Tell me about a project where debugging was part of your work. What did you do?

Adapt your resume

List these exact terms on your resume: Dft, Soc Design, Rtl Design, Testability, and Debugging. An applicant tracking system matches the wording, not the idea.
Attach one line of real, concrete experience to at least one of them. A tool named with nothing behind it rarely survives a human read.

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