Verification Engineer

Intel is hiring a Verification Engineer in Bengaluru, India. Level rates it ; you can apply on Intel.

Level's read on this job

On Level's scale, this role is Little AI ●○○○: aI is not part of the work.
Tools and skills the posting cites include SystemVerilog, UVM and Eda Tools.
Level classifies it as a senior role.
Level lists 823 other open roles at Intel.
The role was posted in the last few days.

AI in this role

Design and execute verification strategies for complex ASIC semiconductor products using SystemVerilog and UVM.

systemveriloguvmeda-tools

asic-designverificationpre-silicon-debuggingtestbench-architecture

Job Details:

Job Description:

Intel is seeking a highly qualified candidate to join our ASIC design verification team in a dynamic and forward-thinking organization focused on next-generation semiconductor product development. Our team focuses on being nimble, adaptable, lean and efficient to drive cutting-edge, customer impacting technology development. We embrace innovative and efficient methodologies that drive at-scale product execution. Advance your career with cutting-edge verification techniques including coverage-driven verification, formal methods, and performance analysis. Lead custom SystemVerilog/UVM development, master industry-standard EDA tools, architect verification strategies for complex ASICs, and mentor emerging talent while independently driving verification closure. Join our fast-paced semiconductor team where your technical leadership shapes next-generation chip development through comprehensive methodologies and innovative verification solutions. Transform challenging projects into career-defining achievements. If you are passionate about building products faster and more efficiently than anyone else on the planet, we want you on our team.

Key Responsibilities:
• Define Project Specific Verification Strategy: Defines and implement scalable and reusable verification plans, test benches, and the verification environments for blocks, subsystems, and SoCs. Ensure meeting the required coverage levels and confirm to microarchitecture specifications.
• Lead Verification Execution: Create detailed test plans and drives technical reviews with design and architecture teams to validate these plans and proofs.
• Executes verification plan: Implement and run block/subsystem/cluster/soc simulation models to verify the design, analyze power and performance, and identify bugs.
• Investigate and Resolve Bugs: Replicates, root causes, and debugs issues in the pre-silicon environment. Finds and implements corrective measures to resolve failing tests.
• Collaborate Across Teams: Work closely with SoC architects, micro architects, full chip architects, RTL developers, post-silicon, and physical design teams to improve verification of complex architectural and microarchitectural features.
• Enhance Future Verification Methodologies: Continuously improves existing functional verification infrastructure and methodologies.
• Absorbs learnings: From post-silicon on the quality of validation done during pre-silicon development, updates test plan for missing coverages and proliferates to future products.
• Lead and mentor others: inspire and guide junior engineers, fostering their growth and development.

Your expertise will be instrumental in cultivating a collaborative and innovative environment where every team member thrives.

Qualifications:

Minimum Qualifications: You must possess the below minimum qualifications to be initially considered for this position. • Bachelor's degree in electrical engineering, computer engineering, computer science, or in other relevant STEM related degree. • 6+ years of experience in ASIC/FPGA design verification • Strong understanding of object-oriented programming (OOP) principles and their application in SystemVerilog UVM or other verification methodologies. • Developing UVM and/or Formal based verification architectures and methodologies. • Experience with industry standard protocols (AMBA AXI/AXI-S/CHI and Low-speed communication protocols (UART, SPI, I2C/I3C)) • Hands-on experience with simulators (Synopsys VCS, Cadence Xcelium, or equivalent). • Familiarity with coverage-driven verification, constrained-random testing and strong debugging skills. • Experience with scripting languages. Preferred Qualifications: • Graduate/post-graduate degree in electrical engineering, computer engineering, computer science, or any STEM related degree with overall 8+ yrs. of experience. • Skilled in various validation concepts and debug techniques relevant to ASIC/FPGA domain. • Collaborative, able to communicate well with counter parts and stakeholders. Strong written and verbal communication skills. • Strong analytical ability and problem-solving skills. • Experience in defining testbench architecture, constrained random verification methodologies. • Experience in processor-based verification using C/C++ with UVM-based verification environments. • Define and execute validation of IPs and/or SOC from spec to tape-in including setting verification strategy, creating test bench and components, defining test plan, writing tests, debugging, coverage and analysis. • Low power experience (e.g., UPF). • Experience in AMBA, CXS stream, DDR, PCIe and/or Ethernet, UCIe protocols. • Experience in EDA tools and reusable testbench for subsystem and SoC that deploys 3rd party VIPs. • Experience with formal verification techniques and tools is an asset.

Job Type:

Experienced Hire

Shift:

Shift 1 (India)

Primary Location:

India, Bangalore

Additional Locations:

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

How we rate this

Verification Engineer at Intel rates 0 out of 100 for how much of the daily work is AI. That makes it Little AI (AI Level 1 of 4). The level is about AI in the job, not seniority.

Classification

Little AI. AI is not part of the work.

●●●● Builds AI80 to 100
●●●○ Works on AI60 to 79
●●○○ Uses AI40 to 59
●○○○ Little AI0 to 39

Levels come from how often the tools, models and workflows of the role are named in the posting itself. Read the description and count the AI tools, models and workflows it names.

Key facts

Verification Engineer is an open job at Intel.
Level rates this role AI Level 1 of 4: Little AI.
The role is based in India, Bangalore.
The job was posted on November 3, 2026.
Seniority: senior.
Applications are handled by Intel. Apply on Intel

Prepare for this job

Built from this posting and from similar jobs on Level.

Skills and AI tools this role asks for

Asic DesignVerificationPre Silicon DebuggingTestbench ArchitectureSystemVerilogUVMEda Tools

Questions you could be asked

Tell me about a project where asic design was part of your work. What did you do?
Tell me about a project where verification was part of your work. What did you do?
Tell me about a project where pre silicon debugging was part of your work. What did you do?
Tell me about a project where testbench architecture was part of your work. What did you do?
Walk me through how you've used SystemVerilog in your day-to-day work.

Adapt your resume

List these exact terms on your resume: Asic Design, Verification, Pre Silicon Debugging, Testbench Architecture, and SystemVerilog. An applicant tracking system matches the wording, not the idea.
Attach one line of real, concrete experience to at least one of them. A tool named with nothing behind it rarely survives a human read.

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