ASIC TOP Floorplan Intern, 2027

NVIDIA is hiring an ASIC TOP Floorplan Intern, 2027 in Shanghai, China. Level rates it ; you can apply on NVIDIA.

Level's read on this job

Level rates this role Little AI ●○○○: aI is not part of the work.
The posting mentions Verilog, System Verilog and Python among its tools and skills.
Level classes it as an internship.
NVIDIA has 2,600+ other open roles on Level.
Posted within the past two weeks.

AI in this role

Design and optimize ASIC floorplans and build physical design infrastructure for next-generation GPUs and SoCs as an intern.

verilogsystem-verilogpythonperlc

asicfloorplanningphysical-designsoc-design

We are now looking for an Intern ASIC TOP Floorplan Design Engineer. NVIDIA is seeking a talented ASIC Floorplan Engineer to design and implement the world’s leading SoC's and GPU's. This position offers you a unique opportunity to craft and to influence the design and development of the next generation GPU and SoC, allowing you to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of exceptional people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing.

What you will be doing:

Working with architects, design leads, physical design leads and package leads, you will develop and to craft and optimize floorplans during early chip development.
Drive the area review process and collaborate with the ASIC design team to identify area, interconnect and floorplan improvement opportunities.
Solve timing and routing congestion issues with physical and ASIC design teams by influencing early design and physical implementation decisions.
You will build tools and improve existing infrastructure to optimize chip area and speed of execution.

What we need to see:

Masters Degree in Electrical Engineering, Computer Science, or Computer Engineering or equivalent work/learning experience.
Experience in Verilog, System Verilog or similar HVL.
Experience with CAD and physical design methodologies (flow and tool development), chip floorplan, power/clock distribution, packaging, P&R and timing closure.
Strong communication and interpersonal skills and ability & desire to work as a great teammate should be displayed in your interview.
Python, Perl and C/C++ programming language experience.

Ways to stand out from the crowd:

Experience in driving development of large scale ASIC floorplan is a huge plus.

NVIDIA is widely considered to be one of the technology world’s most desirable employers. Our products are leading the way with groundbreaking developments in Artificial Intelligence, Autonomous Driving, High-Performance Computing and Visualization. We have some of the most forward-thinking and hardworking people in the world working for us. Are you creative and autonomous? Do you love the challenge of crafting the fastest and most power efficient chips in their class? If so, we want to hear from you.

How we rate this

ASIC TOP Floorplan Intern, 2027 at NVIDIA rates 0 out of 100 for how much of the daily work is AI. That makes it Little AI (AI Level 1 of 4). The level is about AI in the job, not seniority.

Classification

Little AI. AI is not part of the work.

●●●● Builds AI80 to 100
●●●○ Works on AI60 to 79
●●○○ Uses AI40 to 59
●○○○ Little AI0 to 39

Levels come from how often the tools, models and workflows of the role are named in the posting itself. Read the description and count the AI tools, models and workflows it names.

Key facts

ASIC TOP Floorplan Intern, 2027 is an open job at NVIDIA.
Level rates this role AI Level 1 of 4: Little AI.
The role is based in China, Shanghai.
The job was posted on October 19, 2026.
Seniority: intern.
Applications are handled by NVIDIA. Apply on NVIDIA

Prepare for this job

Built from this posting and from similar jobs on Level.

Skills and AI tools this role asks for

AsicFloorplanningPhysical DesignSoc DesignVerilogSystem VerilogPythonPerl

Questions you could be asked

Tell me about a project where asic was part of your work. What did you do?
Tell me about a project where floorplanning was part of your work. What did you do?
Tell me about a project where physical design was part of your work. What did you do?
Tell me about a project where soc design was part of your work. What did you do?
Walk me through how you've used Verilog in your day-to-day work.

Adapt your resume

List these exact terms on your resume: Asic, Floorplanning, Physical Design, Soc Design, and Verilog. An applicant tracking system matches the wording, not the idea.
Attach one line of real, concrete experience to at least one of them. A tool named with nothing behind it rarely survives a human read.

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