DFT Design Engineer, Machine Learning Acceleration

Amazon is hiring a DFT Design Engineer, Machine Learning Acceleration in Austin, United States. It pays $154k-$215k a year and Level rates it ; you can apply on Amazon.

Level's read on this job

Builds AI ●●●● is how Level rates this role: the job is building AI systems.
Tools and skills the posting cites include Verilog, System Verilog and Atpg.
Level classifies it as a senior role.
Level lists 20,000+ other open roles at Amazon.

AI in this role

Design and optimize DFT architectures for custom AWS machine learning acceleration SoCs and server infrastructure.

VerilogSystem VerilogAtpgJtagMbistPythonPerlTcl

asicdfthardware-designmachine-learning-accelerationsoc

Custom SoCs (System on Chip) are at the heart of AWS Machine Learning servers. As a member of the Cloud-Scale Machine Learning Acceleration team, you'll be responsible for designing and optimizing hardware in our data centers, including AWS Inferentia and Trainium systems—our custom-designed machine learning inference and training servers. Our success depends on world-class server infrastructure as we handle massive scale and rapidly integrate emerging technologies. We're looking for an ASIC DFT Design Engineer to help us trailblaze new technologies and architectures while ensuring high design quality and making the right trade-offs.

Key job responsibilities
• Define and develop state-of-the-art Design for Test (DFT) architectures for advanced technology nodes
• Work closely with block designers and physical design (PD) team to implement highly efficient DFT solutions
• Perform RTL coding and Verification using Verilog/System Verilog
• Utilize industry standard DFT tools to create high coverage and cost-effective test patterns to target advanced silicon defects
• Participate in Silicon debug efforts alongside ATE and System teams
• Communicate and work with team members across multiple disciplines

Basic qualifications

- Bachelor's degree in Electrical or Communications Engineering or a related field
- 5+ years of practical DFT experience with complex SoC designs in advanced technology nodes
- Experience with standard tools and practices in DFT, including ATPG, JTAG, MBIST and trade-offs between test quality and test time
- Experience with automation script development

Preferred qualifications

- Master's degree in Electrical or Communications Engineering or a related field
- Practical experience developing STA constraints for DFT modes and working directly with PD teams to close timing
- Experience with RTL coding and design verification (DV) flows
- Experience with gate-level simulation setup and debug with SDF
- Strong programming and scripting skills in Perl, Python or Tcl
- Practical experience with silicon debug and yield optimization

Amazon is an equal opportunity employer and does not discriminate on the basis of protected veteran status, disability, or other legally protected status.

Our inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit https://amazon.jobs/content/en/how-we-hire/accommodations for more information. If the country/region you’re applying in isn’t listed, please contact your Recruiting Partner.

The base salary range for this position is listed below. Your Amazon package will include sign-on payments and restricted stock units (RSUs). Final compensation will be determined based on factors including experience, qualifications, and location. Amazon also offers comprehensive benefits including health insurance (medical, dental, vision, prescription, Basic Life & AD&D insurance and option for Supplemental life plans, EAP, Mental Health Support, Medical Advice Line, Flexible Spending Accounts, Adoption and Surrogacy Reimbursement coverage), 401(k) matching, paid time off, and parental leave. Learn more about our benefits at https://amazon.jobs/en/benefits.

USA, TX, Austin - 153,600.00 - 215,000.00 USD annually

How we rate this

DFT Design Engineer, Machine Learning Acceleration at Amazon rates 80 out of 100 for how much of the daily work is AI. That makes it Builds AI (AI Level 4 of 4). The level is about AI in the job, not seniority.

Classification

Builds AI. The job is building AI systems.

●●●● Builds AI80 to 100
●●●○ Works on AI60 to 79
●●○○ Uses AI40 to 59
●○○○ Little AI0 to 39

Levels come from how often the tools, models and workflows of the role are named in the posting itself. Read the description and count the AI tools, models and workflows it names.

Key facts

DFT Design Engineer, Machine Learning Acceleration is an open job at Amazon.
Level rates this role AI Level 4 of 4: Builds AI.
The listed salary is $154k-$215k a year.
The role is based in US, TX, Austin.
The job was posted on September 1, 2026.
Seniority: senior.
Applications are handled by Amazon. Apply on Amazon

Prepare for this job

Built from this posting and from similar jobs on Level.

Skills and AI tools this role asks for

AsicDftHardware DesignMachine Learning AccelerationSocVerilogSystem VerilogAtpg

Questions you could be asked

Tell me about a project where asic was part of your work. What did you do?
Tell me about a project where dft was part of your work. What did you do?
Tell me about a project where hardware design was part of your work. What did you do?
Tell me about a project where machine learning acceleration was part of your work. What did you do?
Tell me about a project where soc was part of your work. What did you do?

Adapt your resume

List these exact terms on your resume: Asic, Dft, Hardware Design, Machine Learning Acceleration, and Soc. An applicant tracking system matches the wording, not the idea.
Attach one line of real, concrete experience to at least one of them. A tool named with nothing behind it rarely survives a human read.
Lead with what you built, trained or shipped. This role is judged on the AI system itself, not the tools around it.

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