E-core CPU Layout Design Engineer

Intel is hiring an E-core CPU Layout Design Engineer. Level rates it ; you can apply on Intel.

Level's read on this job

On Level's scale, this role is Little AI ●○○○: aI is not part of the work.
Level classes it as a senior role.
Intel has 746 other open roles on Level.
Posted in the last few days.

AI in this role

Job Details:

Job Description:

The Role and Impact As an E-Core (Atom) CPU Layout Design Engineer, you will play a pivotal role in shaping the physical layout of Intel's cutting-edge Atom processors, contributing to high-performance products that drive a wide range of applications. In this role, you'll focus on implementing custom layouts for analog blocks, digital designs, and memory compilers, ensuring compliance with design specifications and reliability criteria. Your work will directly impact Intel's ability to deliver innovative microprocessor solutions to the market. Business group Join Intel Corporation's Atom Layout Design team, a group dedicated to advancing Intel Atom processors (E-Core), which power a diverse array of products spanning entry-level PCs, smartphones, laptops, and IoT devices. This team plays a crucial role in supporting Intel's mission to deliver high-performance, energy-efficient solutions that drive technological innovation and global connectivity. Key Responsibilities - Drive custom layout design for memory compilers, custom IPs, and partitions supporting CPU products. - Perform physical array planning, area optimization, and critical wire analysis to ensure efficient designs. - Conduct complete layout verification, including design rule compliance, SoC integration standards, and reliability checks such as electron migration, voltage drop (IR), and self-heating. - Utilize custom autorouters and placers for layout construction while innovating new methods to improve productivity and design quality. - Collaborate closely with circuit design engineers to assess feasibility, provide feedback, and implement circuit enhancement requests. - Troubleshoot design, tool flow, and methodology issues to ensure seamless implementation and integration. - Partner with cross-site teams to align on design strategies, reuse methodologies, and project consistency.

Qualifications:

Minimum Qualifications: - Bachelor's or Master's degree in Electronics/Microelectronics Engineering, Computer Engineering, or a related discipline with 9+ years of experience in layout design. - Proficiency in Very Large Scale Integration (VLSI) and Complementary Metal-Oxide Semiconductor (CMOS) logic circuit design. - Programming skills in UNIX shell scripting, TCL, and Perl. Preferred Qualifications - Strong communication and collaboration skills demonstrated through team projects or leadership experience. - Ability to propose and implement innovative solutions to enhance design productivity and quality. We encourage you to explore this exciting opportunity to impact Intel's next-generation technologies. Your contributions will help shape the future of computing and innovation.

Job Type:

Experienced Hire

Shift:

Shift 1 (Malaysia)

Primary Location:

Malaysia, Penang

Additional Locations:

Malaysia, Kulim

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

How we rate this

E-core CPU Layout Design Engineer at Intel rates 26 out of 100 for how much of the daily work is AI. That makes it Little AI (AI Level 1 of 4). The level is about AI in the job, not seniority.

Classification

Little AI. AI is not part of the work.

●●●● Builds AI80 to 100
●●●○ Works on AI60 to 79
●●○○ Uses AI40 to 59
●○○○ Little AI0 to 39

Levels come from how often the tools, models and workflows of the role are named in the posting itself. Read the description and count the AI tools, models and workflows it names.