FPGA Verification Engineer

In an increasingly connected world, the pandemic has highlighted just how essential telecom networks are to keeping society running. The Network Infrastructure group is at the heart of a revolution to connectivity, pushing the boundaries to deliver more and faster network capacity to people worldwide through our ambition, innovation, and technical expertise

 Join Optical Networks division, where innovation meets scale in the AI-driven data center era. With the recent acquisition of Infinera, we’ve united two industry leaders to create an optical networking powerhouse—combining cutting-edge technology with proven leadership to redefine the future of connectivity.

Infinera is now part of the Nokia Corporation and its subsidiaries. When you apply, the information you share will be handled with care and used only for recruitment purposes within the group. 

As an FPGA Verification engineer, you will be responsible for designing verification plans, developing environment/testbench, creating test scenarios for running simulations, coverage analysis and lab support during board bring up to ensure first time right quality of Infinera product. Candidate should be capable of handling projects independently and have a strong will to drive for solutions.

• Develop and execute verification plans for high-complexity DWDM systems used in LH/ULH optical network applications.
• Design and implement simulation environments and testbenches to validate FPGA functionality and performance.
• Create and run functional and directed/random test scenarios to ensure comprehensive design coverage.
• Perform detailed coverage analysis and implement strategies to achieve full functional and code coverage.
• Collaborate closely with cross-functional R&D teams across multiple global locations throughout the product lifecycle.
• Provide lab support during board bring-up and assist in root cause analysis to ensure first-time-right product quality.
• Independently manage verification projects with a proactive and solution-driven approach to meet quality and timeline goals.

• Must have 12 – 16 years of experience in developing System Verilog UVM based test environments, developing and implementing test plans – at block, sub-chip and chip levels.
• Must have strong HVL coding skills for Verification and be hands-on with one or more Industry standard simulators such as VCS, NC, MTI used in Verification and waveform-based debugging tools.
• Exposure to UVM (or similar) verification methodologies is required.
• Familiarity with HDLs such as Verilog and scripting languages such as perl is highly desired. Working knowledge of RTL design is preferred.
• Should be conversant with technologies like the Ethernet, PCIe, I2C, SPI etc. Knowledge of telecom protocol is preferred.
• Structured and thorough with analytical and troubleshooting skills.
• Good written and oral communication skills are required.
• Flexible, innovative, self-driven and willing to take initiatives.
• Highly motivated team player with exceptional leadership capability.