Physical Design Clocking Engineer

Intel is hiring a Physical Design Clocking Engineer in Santa Clara, United States. It pays $106k-$149k a year and Level rates it ; you can apply on Intel.

Level's read on this job

On Level's scale, this role is Little AI ●○○○: aI is not part of the work.
The posting mentions Eda Software, Synthesis Tools and Static Timing Analysis among its tools and skills.
Level classes it as a junior role.
Intel has 842 other open roles on Level.
Posted within the past week.

AI in this role

Physical design clocking engineer responsible for implementing custom IP and SoC designs from RTL to GDS with focus on optimization.

Eda SoftwareSynthesis ToolsStatic Timing Analysis

physical-designsocrtl-to-gdsclock-tree-synthesisfloorplanning

Job Details:

Job Description:

As a Physical Design Engineer, you will play a critical role in the implementation of custom IP and SoC designs, transforming RTL to GDS to produce design databases ready for manufacturing. On a day-to-day basis, you will execute various aspects of the physical design flow, including synthesis, place and route, clock tree synthesis, floor planning, and static timing analysis. Your work will directly contribute to optimizing design parameters such as power, frequency, and area, impacting Intel's product innovation and delivery.

You will be part of the Data Center Group (DCG), a business unit focused on developing innovative solutions that power the future of computing. DCG works on designing advanced technologies for data centers, cloud services, and high-performance computing environments, enabling Intel's broader mission to shape the future of technology. This team provides a collaborative environment driven by technical excellence and a passion for innovation.

The primary responsibilities for this role will include, but are not limited to:

Conduct physical design implementation tasks, including synthesis, place and route, clock tree synthesis, floor planning, and static timing analysis.
Perform verification and signoff activities, such as equivalence verification, reliability verification, layout verification, and structural design checking.
Analyze results and provide recommendations to resolve violations for current and future architectures.
Optimize designs to improve product level parameters, including power, frequency, and area. -
Participate in developing and enhancing physical design methodologies, flows, and automation processes.
Utilize industry-standard EDA tools to execute and validate physical design processes effectively.

Qualifications:

Minimum Qualifications:

Minimum qualifications are required to be initially considered for this position.

Bachelor's degree in a relevant field with 0-1 years of hands-on experience in physical design, demonstrating skills gained through internships, academic projects, coursework, or hands-on training OR a Master's degree in a relevant field with no prior professional experience.
Proficiency in physical design tools, such as synthesis, place and route, and timing analysis software.
Familiarity with EDA tools and methodologies used in physical design and verification workflows.

Preferred Qualifications:

Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Strong analytical and problem-solving skills to identify and resolve design violations effectively.
Excellent communication and collaboration abilities to contribute within a dynamic team environment.
A proactive mindset and eagerness to learn and improve physical design methodologies and flows.

Join us in shaping the future of data-centric technology by applying your skills, curiosity, and passion for innovation.

Job Type:

College Grad

Shift:

Shift 1 (United States of America)

Primary Location:

US, California, Santa Clara

Additional Locations:

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $105,650.00-149,150.00 USD

The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

How we rate this

Physical Design Clocking Engineer at Intel rates 0 out of 100 for how much of the daily work is AI. That makes it Little AI (AI Level 1 of 4). The level is about AI in the job, not seniority.

Classification

Little AI. AI is not part of the work.

●●●● Builds AI80 to 100
●●●○ Works on AI60 to 79
●●○○ Uses AI40 to 59
●○○○ Little AI0 to 39

Levels come from how often the tools, models and workflows of the role are named in the posting itself. Read the description and count the AI tools, models and workflows it names.

Key facts

Physical Design Clocking Engineer is an open job at Intel.
Level rates this role AI Level 1 of 4: Little AI.
The listed salary is $106k-$149k a year.
The role is based in US, California, Santa Clara.
The job was posted on November 3, 2026.
Seniority: junior.
Applications are handled by Intel. Apply on Intel

Prepare for this job

Built from this posting and from similar jobs on Level.

Skills and AI tools this role asks for

Physical DesignSocRtl To GdsClock Tree SynthesisFloorplanningEda SoftwareSynthesis ToolsStatic Timing Analysis

Questions you could be asked

Tell me about a project where physical design was part of your work. What did you do?
Tell me about a project where soc was part of your work. What did you do?
Tell me about a project where rtl to gds was part of your work. What did you do?
Tell me about a project where clock tree synthesis was part of your work. What did you do?
Tell me about a project where floorplanning was part of your work. What did you do?

Adapt your resume

List these exact terms on your resume: Physical Design, Soc, Rtl To Gds, Clock Tree Synthesis, and Floorplanning. An applicant tracking system matches the wording, not the idea.
Attach one line of real, concrete experience to at least one of them. A tool named with nothing behind it rarely survives a human read.

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