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NVIDIA

Senior ASIC Design Engineer - NOC IP

NVIDIA is hiring a Senior ASIC Design Engineer - NOC IP in Bengaluru, India. Level rates it ; you can apply on NVIDIA.

Level's read on this job

  • On Level's scale, this role is Little AI ●○○○: aI is not part of the work.
  • The posting mentions Verilog, Vcs and Debussy among its tools and skills.
  • Level classes it as a senior role.
  • NVIDIA has 2,700+ other open roles on Level.

AI in this role

Design and verify state-of-the-art memory subsystem components and network interconnect IP for NVIDIA graphics processors.

verilogvcsdebussygdbpythonperl
asic-designrtlmicro-architecturedebugginglogic-synthesis

NVIDIA is seeking passionate, highly motivated, and creative senior design engineers to be part of its Graphics team working on the design of state of the art memory subsystem components used in their industry-leading Graphics Processors. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of exceptional people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing.

In this position, you will be expected to make architectural trade-offs based on features, performance requirements and system limitations, come up with micro-architecture, implement in RTL, and deliver a fully verified, synthesis/timing clean design. You will work with architects, other designers, pre- and post-silicon verification teams, synthesis, timing and backend teams to accomplish your tasks.

What you’ll be doing:

  • Own micro-architecture and RTL development of design modules.

  • Micro-architect features to meet performance, power and area requirements.

  • Work with HW architects to define critical features.

  • Collaborate with verification teams to verify the correctness of implemented features.

  • Co-operate with timing, VLSI and Physical design teams to ensure design meets timing, interface requirements and is routable.

  • Interact with FPGA and S/W teams to prototype the design and ensure that S/W is tested.

  • Work on post-silicon verification and debug.

What we need to see:

  • BS / MS or equivalent experience.

  • 7+ years of design experience.

  • Experience in RTL design of complex design units for at least two or three projects.

  • Exposure to design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy, GDB).

  • Deep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, bring-up & lab debug.

  • Expertise in Verilog.

Ways to stand out from the crowd:

  • Design experience in memory subsystem or network interconnect IP.

  • Good debugging and problem solving skills.

  • Scripting knowledge (Python/Perl/shell).

  • Leadership experience in leading small 2-3 member teams.

  • Good interpersonal skills and ability & desire to work as a part of a team.

NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most brilliant and talented people in the world working for us. If you are creative, autonomous and love a challenge, we want to hear from you.

We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.

#LI-Hybrid

How we rate this

Senior ASIC Design Engineer - NOC IP at NVIDIA rates 10 out of 100 for how much of the daily work is AI. That makes it Little AI (AI Level 1 of 4). The level is about AI in the job, not seniority.

Classification

Little AI. AI is not part of the work.

  1. ●●●● Builds AI80 to 100
  2. ●●●○ Works on AI60 to 79
  3. ●●○○ Uses AI40 to 59
  4. ●○○○ Little AI0 to 39

Levels come from how often the tools, models and workflows of the role are named in the posting itself. Read the description and count the AI tools, models and workflows it names.

Prepare for this job

Built from this posting and from similar jobs on Level.

Skills and AI tools this role asks for

Asic DesignRtlMicro ArchitectureDebuggingLogic SynthesisVerilogVcsDebussy

Questions you could be asked

  1. Tell me about a project where asic design was part of your work. What did you do?
  2. Tell me about a project where rtl was part of your work. What did you do?
  3. Tell me about a project where micro architecture was part of your work. What did you do?
  4. Tell me about a project where debugging was part of your work. What did you do?
  5. Tell me about a project where logic synthesis was part of your work. What did you do?

Adapt your resume

  • List these exact terms on your resume: Asic Design, Rtl, Micro Architecture, Debugging, and Logic Synthesis. An applicant tracking system matches the wording, not the idea.
  • Attach one line of real, concrete experience to at least one of them. A tool named with nothing behind it rarely survives a human read.

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