Senior Circuit Design Engineer
Cisco is hiring a Senior Circuit Design Engineer. Level rates it ; you can apply on Cisco.
Level's read on this job
- Little AI ●○○○ is how Level rates this role: aI is not part of the work.
- Level classifies it as a senior role.
- Level lists 1,500+ other open roles at Cisco.
- The role was posted in the last few days.
AI in this role
As part of the team behind Cisco Silicon One—the industry’s only unified silicon architecture spanning top-of-rack switches to web-scale data centers—you’ll help shape Cisco’s groundbreaking solutions by designing, developing, and testing some of the most advanced ASICs in the industry. Our international group focuses on groundbreaking process technology to ensure the efficiency and performance of our ASIC products.
Your Impact
As an ASIC Circuit Design Engineer, you will own the end-to-end development of high-performance ASIC subsystems and reusable IP. You will contribute to achieving aggressive power, performance, area, and reliability goals by developing custom digital and analog/mixed-signal blocks. You will work closely with architecture, physical design, and silicon validation teams to ensure our IP is optimized for the next generation of networking silicon, while employing automation to drive quality and productivity across the entire product lifecycle.
Key Responsibilities
- Drive the architecture, design, and implementation of high-performance ASIC subsystems and IP from specification through silicon validation.
- Develop and productize standard-cell, custom digital, and analog/mixed-signal IP to meet strict performance and robustness requirements.
- Perform transistor-level simulation and optimization, accounting for process, voltage, temperature, and aging conditions.
- Define and implement characterization methodologies for standard-cell and mixed-signal models, including the deployment of automated EDA flows.
- Collaborate with multi-functional teams, including physical design and system architecture, to define interface requirements and implementation constraints.
- Own the physical implementation of complex custom blocks, optimizing for timing, power, signal integrity, and layout-dependent effects.
- Analyze silicon results post-bring-up to drive improvements in circuit design, characterization models, and future IP architectures.
- Drive technical reviews for schematics, layouts, and methodologies to resolve complex cross-disciplinary issues and mitigate architectural risks.
- Develop reusable infrastructure, scripts, and documentation to improve engineering productivity and design quality.
- Apply expertise in advanced process nodes, including FinFET and GAA, to push the boundaries of ASIC power-delivery and clocking solutions.
Minimum Qualifications
- Bachelor’s degree and 7 years of related experience, or Master’s degree plus 4 years of related experience, or PhD plus 1 year of related experience.
- Relevant experience should include ASIC, custom digital, standard-cell, or analog/mixed-signal circuit design and implementation.
Preferred Qualifications
- Design & IP Development: Proven expertise in designing and optimizing custom digital circuits (e.g., standard cells, low-power cells) and analog/mixed-signal IP (e.g., regulators, oscillators, sensors) with a strict focus on PPA, reliability, and yield.
- Methodology & Analysis: Strong background in circuit-level analysis (SPICE, PVT, Monte Carlo, variation) and standard-cell modeling (Liberty, CCS/ECSM, LVF) using industry-standard EDA tools from Cadence, Synopsys, or Siemens.
- Physical & Process Implementation: First-hand experience with advanced nodes (FinFET/GAA) and physical implementation flows, including custom layout, parasitic extraction, DRC/LVS, and reliability analysis (EM/IR).
- Silicon Lifecycle & Leadership: Demonstrated ability to lead technical reviews, influence ASIC architecture, and get results through silicon bring-up, failure analysis, and model-to-silicon correlation.
- Proficiency in automation and scripting (Python, Tcl, or shell) to enhance engineering productivity.
At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.
Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.
We are Cisco, and our power starts with you.
How we rate this
Senior Circuit Design Engineer at Cisco rates 20 out of 100 for how much of the daily work is AI. That makes it Little AI (AI Level 1 of 4). The level is about AI in the job, not seniority.
Little AI. AI is not part of the work.
- ●●●● Builds AI80 to 100
- ●●●○ Works on AI60 to 79
- ●●○○ Uses AI40 to 59
- ●○○○ Little AI0 to 39
Levels come from how often the tools, models and workflows of the role are named in the posting itself. Read the description and count the AI tools, models and workflows it names.
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