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Cisco

Senior Physical Design CAD

Cisco is hiring a Senior Physical Design CAD. Level rates it ; you can apply on Cisco.

Level's read on this job

  • Little AI ●○○○ is how Level rates this role: aI is not part of the work.
  • Tools and skills the posting cites include Synopsys, Cadence and physical design.
  • Level classifies it as a senior role.
  • Level lists 1,400+ other open roles at Cisco.
  • The role was posted within the past two weeks.

AI in this role

Drive backend methodology, CAD tools, and physical design flows for Cisco Silicon One network ASICs.

synopsyscadence
physical-designvlsicadasicplace-and-route

Job Description

Silicon One is seeking a CAD Engineer to join the Cisco Silicon One Physical Design team.


Meet the Team

You'll be part of the Cisco Silicon One team, which is at the heart of Cisco’s software and ASIC design efforts.

As part of our team, you’ll contribute to the development of our next-generation network devices—Cisco Silicon One™. Our team operates in a startup-like environment within a stable and leading corporation.

Our design center is uniquely equipped, hosting all silicon hardware and software development fields under one roof.

We are revolutionizing the industry by building a new internet for the 5G era, providing a unified, programmable silicon architecture that serves as the foundation for all of Cisco's future routing products. Our devices are designed to be universally adaptable across service providers and web-scale markets, catering to both fixed and modular platforms. They deliver high speed without compromising on programmability, buffering, power efficiency, scale, or feature flexibility.

Cisco Silicon One is a ground-breaking, groundbreaking technology that will serve our customers and end users for decades to come. The Internet now has a new, faster, better, and safer engine!


Your Impact

You'll be joining our Physical Design team within Cisco Silicon One, which is responsible for the entire backend methodology and flow development from RTL to GDS. This is a critical part of the group leading the development of high-quality VLSI designs.

Our Backend Engineers handle all aspects of chip design, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning.

You will be leveraging your backend and physical design experience to drive the development, optimization, and innovation of CAD methodologies and tools, ensuring the highest quality and efficiency in our chip design flows from RTL to GDS.


Minimum Qualifications

  • A VLSI Design Engineer with extensive experience in backend design
  • B.Sc./M.Sc. in Electrical Engineering or Computer Engineering with relevant background.
  • 7+ years of hands-on experience in a relevant domain
  • Strong understanding of Place & Route flow

Preferred Qualifications

  • Deep understanding of Physical construction and Integration.
  • Knowledge of Physical Design Verification methods like LVS/DRC and formal verification.
  • Experience with PD CAD and Physical Design EDA tools (e.g., Synopsys, Cadence).
  • Ability to support technology adoption and new tool integration.
  • Great teammate, self-learner, and able to work independently.

Why Cisco?

At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.

Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.

We are Cisco, and our power starts with you.

How we rate this

Senior Physical Design CAD at Cisco rates 0 out of 100 for how much of the daily work is AI. That makes it Little AI (AI Level 1 of 4). The level is about AI in the job, not seniority.

Classification

Little AI. AI is not part of the work.

  1. ●●●● Builds AI80 to 100
  2. ●●●○ Works on AI60 to 79
  3. ●●○○ Uses AI40 to 59
  4. ●○○○ Little AI0 to 39

Levels come from how often the tools, models and workflows of the role are named in the posting itself. Read the description and count the AI tools, models and workflows it names.

Prepare for this job

Built from this posting and from similar jobs on Level.

Skills and AI tools this role asks for

Physical DesignVlsiCADAsicPlace And RouteSynopsysCadence

Questions you could be asked

  1. Tell me about a project where physical design was part of your work. What did you do?
  2. Tell me about a project where vlsi was part of your work. What did you do?
  3. Tell me about a project where cad was part of your work. What did you do?
  4. Tell me about a project where asic was part of your work. What did you do?
  5. Tell me about a project where place and route was part of your work. What did you do?

Adapt your resume

  • List these exact terms on your resume: Physical Design, Vlsi, CAD, Asic, and Place And Route. An applicant tracking system matches the wording, not the idea.
  • Attach one line of real, concrete experience to at least one of them. A tool named with nothing behind it rarely survives a human read.

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