Silicon Packaging Design Engineer

Intel is hiring a Silicon Packaging Design Engineer in Bengaluru, India. Level rates it ; you can apply on Intel.

Level's read on this job

On Level's scale, this role is Little AI ●○○○: aI is not part of the work.
The posting mentions Siemens Xpedition, ic packaging and substrate design among its tools and skills.
Level classes it as a senior role.
Intel has 842 other open roles on Level.
Posted within the past two weeks.

AI in this role

Define and design custom IC packaging solutions ensuring optimal mechanical, thermal, and electrical performance.

Siemens Xpedition

ic-packagingsubstrate-designthermal-analysiselectrical-simulation

Job Details:

Job Description:

Define packaging solutions for highly innovative integrated circuits, meeting adequate mechanical, thermal and electrical performance with the goal to achieve lowest package and system level cost. Co-design with chip designer, system engineering and PCB design teams during the development stage to optimize pad layout and pin map for most cost effective package and system. Independently plan, design and develop quality custom lead frame/substrate/module with supporting electrical simulation to reduce cross-talk, IR drop, and noise issues of the device. Technical lead for implementing packaging solutions at OSAT assembly site and/or internal assembly site. Ensure optimized package design which meets the assembly design rules of the selected assembly site. Work with the assembly partner to mitigate any potential risk and improve situation to meet yield target within the project milestone requirement. Co-work with NPI manager to prepare assembly site readiness for continuous uninterrupted flow from wafer fab-out to quality packaged sample meeting the required NPI schedule. Maintain complete set of product specific packaging related drawings, and reports.

Qualifications:

Bachelor / Master degree in Electrical Engineering / Mechanical Engineering / Material Science with more than 10 years experience in the field of IC Packaging Design and Layout. Package design experience using Siemens Xpedition EDA tool set is a must. Understand performance and cost trade-offs for different layout and assembly rules. Extensive manufacturing process knowledge regarding wafer bumping, substrate and lead frame manufacturing and assembly of wire bond and flip chip packages is required. Practical knowledge of Signal integrity and Power integrity in PCB design will be an advantage. Possesses good analytical, communication and organization skills.

Job Type:

Intel Contract Employee

Shift:

Shift 1 (India)

Primary Location:

India, Bangalore

Additional Locations:

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

How we rate this

Silicon Packaging Design Engineer at Intel rates 0 out of 100 for how much of the daily work is AI. That makes it Little AI (AI Level 1 of 4). The level is about AI in the job, not seniority.

Classification

Little AI. AI is not part of the work.

●●●● Builds AI80 to 100
●●●○ Works on AI60 to 79
●●○○ Uses AI40 to 59
●○○○ Little AI0 to 39

Levels come from how often the tools, models and workflows of the role are named in the posting itself. Read the description and count the AI tools, models and workflows it names.

Key facts

Silicon Packaging Design Engineer is an open job at Intel.
Level rates this role AI Level 1 of 4: Little AI.
The role is based in India, Bangalore.
The job was posted on October 26, 2026.
Seniority: senior.
Applications are handled by Intel. Apply on Intel

Prepare for this job

Built from this posting and from similar jobs on Level.

Skills and AI tools this role asks for

Ic PackagingSubstrate DesignThermal AnalysisElectrical SimulationSiemens Xpedition

Questions you could be asked

Tell me about a project where ic packaging was part of your work. What did you do?
Tell me about a project where substrate design was part of your work. What did you do?
Tell me about a project where thermal analysis was part of your work. What did you do?
Tell me about a project where electrical simulation was part of your work. What did you do?
Walk me through how you've used Siemens Xpedition in your day-to-day work.

Adapt your resume

List these exact terms on your resume: Ic Packaging, Substrate Design, Thermal Analysis, Electrical Simulation, and Siemens Xpedition. An applicant tracking system matches the wording, not the idea.
Attach one line of real, concrete experience to at least one of them. A tool named with nothing behind it rarely survives a human read.

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