Sr. ASIC Design Verification Engineer
Cisco is hiring a Sr. ASIC Design Verification Engineer in San Jose, United States. It pays $168k-$245k a year and Level rates it ; you can apply on Cisco.
Level's read on this job
- Little AI ●○○○ is how Level rates this role: aI is not part of the work.
- Level classifies it as a senior role.
- Level lists 1,400+ other open roles at Cisco.
- The role was posted in the last few days.
AI in this role
Meet the Team
Join the Cisco Silicon One team in developing a unified silicon architecture for web scale and service provider networks. Cisco’s silicon team provides a unique experience for ASIC engineers by combining the resources offered by a large multi-geography silicon organization and a large campus (with onsite gym, healthcare, and café, social interest groups, and philanthropy), with the startup culture and breadth of growth opportunities that working in a smaller ASIC team can provide.
Your Impact
Participate in the ASIC design verification for Cisco high-end switching products.
Architect, develop, and maintain block, cluster, and top-level Design Verification (DV) environment infrastructure
Develop simulation models, test plans, direct and random tests, code or functional coverage, multi-chip/system simulation, and performance analysis.
Construct testbenches components like scoreboard, agents, sequencers, and monitors.
Collaborate with designers, architects, and software teams to debug issues during post-silicon bring-up and integration
Ensure comprehensive verification coverage through code and functional coverage implementation and review
Minimum Qualifications:
Bachelor's degree in electrical/computer science/computer engineering/related degree and 7+ years of related experience or Master's in electrical/computer science/computer engineering/related degree and 4+ years of related experience, or PhD in electrical/computer science/computer engineering/related degree + 1 year of related experience.
Prior experience in System Verilog and UVM.
Experience with ASIC design and verification processes, debugging, methodology, and tools.
Experience in verifying blocks/clusters or full chip level for ASIC.
Preferred Qualifications:
Hands-on experience with Ethernet protocols and high-speed SerDes interfaces
Proficiency in Linux and programming languages such as C/C++ and/or Python/Perl
Strong understanding of networking fundamentals and system-level architectures
Working knowledge of PCIe and AXI protocols
Experience with post-silicon bring-up and lab debugging
Experience in data center, hyperscalers, or AI networking environments
Proven contributions to industry standards or ASIC verification best practices
Deep expertise in multiple protocols and large-scale SoC architectures
At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.
Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.
We are Cisco, and our power starts with you.
Message to applicants applying to work in the U.S. and/or Canada:The starting salary range posted for this position is $167,700.00 to $245,200.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits.Individual pay is determined by the candidate's hiring location, market conditions, job-related skillset, experience, qualifications, education, certifications, and/or training. The full salary range for certain locations is listed below. For locations not listed below, the recruiter can share more details about compensation for the role in your location during the hiring process.
U.S. employees are offered benefits, subject to Cisco’s plan eligibility rules, which include medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, paid parental leave, short and long-term disability coverage, and basic life insurance. Please see the Cisco careers site to discover more benefits and perks. Employees may be eligible to receive grants of Cisco restricted stock units, which vest following continued employment with Cisco for defined periods of time.
U.S. employees are eligible for paid time away as described below, subject to Cisco’s policies:
10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees
1 paid day off for employee’s birthday, paid year-end holiday shutdown, and 4 paid days off for personal wellness determined by Cisco
Non-exempt employees** receive 16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full-time employees
Exempt employees participate in Cisco’s flexible vacation time off program, which has no defined limit on how much vacation time eligible employees may use (subject to availability and some business limitations)
80 hours of sick time off provided on hire date and each January 1st thereafter, and up to 80 hours of unused sick time carried forward from one calendar year to the next
Additional paid time away may be requested to deal with critical or emergency issues for family members
Optional 10 paid days per full calendar year to volunteer
For non-sales roles, employees are also eligible to earn annual bonuses subject to Cisco’s policies.
Employees on sales plans earn performance-based incentive pay on top of their base salary, which is split between quota and non-quota components, subject to the applicable Cisco plan. For quota-based incentive pay, Cisco typically pays as follows:
.75% of incentive target for each 1% of revenue attainment up to 50% of quota;
1.5% of incentive target for each 1% of attainment between 50% and 75%;
1% of incentive target for each 1% of attainment between 75% and 100%; and
Once performance exceeds 100% attainment, incentive rates are at or above 1% for each 1% of attainment with no cap on incentive compensation.
For non-quota-based sales performance elements such as strategic sales objectives, Cisco may pay 0% up to 125% of target. Cisco sales plans do not have a minimum threshold of performance for sales incentive compensation to be paid.
The applicable full salary ranges for this position, by specific state, are listed below:
New York City Metro Area:
$167,700.00 - $282,000.00Non-Metro New York state & Washington state:
$149,100.00 - $250,900.00* For quota-based sales roles on Cisco’s sales plan, the ranges provided in this posting include base pay and sales target incentive compensation combined.
** Employees in Illinois, whether exempt or non-exempt, will participate in a unique time off program to meet local requirements.
How we rate this
Sr. ASIC Design Verification Engineer at Cisco rates 33 out of 100 for how much of the daily work is AI. That makes it Little AI (AI Level 1 of 4). The level is about AI in the job, not seniority.
Little AI. AI is not part of the work.
- ●●●● Builds AI80 to 100
- ●●●○ Works on AI60 to 79
- ●●○○ Uses AI40 to 59
- ●○○○ Little AI0 to 39
Levels come from how often the tools, models and workflows of the role are named in the posting itself. Read the description and count the AI tools, models and workflows it names.
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