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NVIDIA

STA Engineer

NVIDIA is hiring an STA Engineer. Level rates it ; you can apply on NVIDIA.

Level's read on this job

  • Little AI ●○○○ is how Level rates this role: aI is not part of the work.
  • Tools and skills the posting cites include Synopsys, Cadence and static timing analysis.
  • Level classifies it as a mid-level role.
  • Level lists 2,600+ other open roles at NVIDIA.

AI in this role

STA Physical Design Engineer responsible for timing closure and validation of high-speed communication hardware.

synopsyscadence
static-timing-analysisphysical-designdftasic

NVIDIA is looking for best-in-class STA (Static Timing analysis) Physical Design Engineers to join our outstanding Networking DFT team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.

What you will be doing:

  • DFT STA execution, from rtl driven constraints and definitions through DFT constraints quality assurance to STA sign-off.
  • Be part of a unique team of experts who have deep understanding in all aspects of pre and post silicon.
  • Be exposed and work on a variety of challenging designs, unique DFT solutions that require deep silicon implementation understanding.
  • Daily work involves all aspects of static timing analysis - constraints, environment, models generation and timing ECO generation for block level and full chip level.
  • Taking part in flows development.

What we need to see:

  • B.SC. in Electrical Engineering/Computer Engineering.
  • 2-3 years of experience as STA engineer.
  • Ability to quickly adapt to new technology and go deep into new areas
  • Strong communication skills
  • Great teammate.
  • Drive new solutions based on any issues that arise

Ways to Stand Out From the Crowd:

  • Knowledge in physical design flows and methodologies (PNR, STA, physical verification).
  • Knowledge in DFT flows such as ATPG, Mbist, Ijtag.
  • Prior experience in DFT timing closures.
  • Knowledge in CDC.
  • Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.).

NVIDIA has some of the most forward-thinking people in the world working for us. Are you a creative and autonomous engineer who loves a challenge? Are you ready to become the engineer you always wanted to be? Come and be part of the best physical design team in the industry!

How we rate this

STA Engineer at NVIDIA rates 10 out of 100 for how much of the daily work is AI. That makes it Little AI (AI Level 1 of 4). The level is about AI in the job, not seniority.

Classification

Little AI. AI is not part of the work.

  1. ●●●● Builds AI80 to 100
  2. ●●●○ Works on AI60 to 79
  3. ●●○○ Uses AI40 to 59
  4. ●○○○ Little AI0 to 39

Levels come from how often the tools, models and workflows of the role are named in the posting itself. Read the description and count the AI tools, models and workflows it names.

Prepare for this job

Built from this posting and from similar jobs on Level.

Skills and AI tools this role asks for

Static Timing AnalysisPhysical DesignDftAsicSynopsysCadence

Questions you could be asked

  1. Tell me about a project where static timing analysis was part of your work. What did you do?
  2. Tell me about a project where physical design was part of your work. What did you do?
  3. Tell me about a project where dft was part of your work. What did you do?
  4. Tell me about a project where asic was part of your work. What did you do?
  5. Walk me through how you've used Synopsys in your day-to-day work.

Adapt your resume

  • List these exact terms on your resume: Static Timing Analysis, Physical Design, Dft, Asic, and Synopsys. An applicant tracking system matches the wording, not the idea.
  • Attach one line of real, concrete experience to at least one of them. A tool named with nothing behind it rarely survives a human read.

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