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ASIC Engineering Design Verification Leader (SystemVerilog, Python, C and UVM |8-12 years| Pune)

Cisco is hiring an ASIC Engineering Design Verification Leader (SystemVerilog, Python, C and UVM |8-12 years| Pune) (India). Level rates it ; you can apply on Cisco.

Level's read on this job

  • Little AI ●○○○ is how Level rates this role: aI is not part of the work.
  • The posting mentions SystemVerilog, Python and C among its tools and skills.
  • Level classes it as a senior role.
  • Cisco has 1,400+ other open roles on Level.

AI in this role

Lead ASIC design verification using SystemVerilog, UVM, and Python for high-speed optical transceivers and data center networking solutions.

SystemVerilogPythonCUVMFPGA
asic-verificationchip-verificationtestbench-developmentfunctional-coveragedebugging

Meet the Team

Cisco’s Client Optics Group (COG) designs & delivers the high-speed optical transceivers, and platforms that power Cisco's core data center networking solutions. We specialize in the design and integration of cutting-edge IM/DD optics and silicon photonic platforms that enable customers to deploy industry-leading optical technologies within data center with unprecedented speed, capacity, and reliability. Come join us and take part in shaping COG’s ground-breaking optical solutions by designing, developing, and testing some of the most advanced pluggable, and Co-packaged Optics (CPO) being developed in the industry.

You will work with Cisco's outstanding Silicon Photonics team. Our team is responsible for driving the development and optimization of optical transceivers & modules (800G,1.6T & beyond) that seamlessly integrate with Cisco's routing, switching, and datacenter platforms, enabling customers to build scalable, high-performance networks that support emerging technologies including AI/ML workloads, and next-generation data center architectures.

Your Impact

As a Verification Engineer, you will work with a diverse team of engineers spanning multiple disciplines. At the concept phase you will create verification documentation and work with senior engineers to help with defining the verification methodology and developing testbench components. During the initial design phase, you will be a part of block level verification and then you will transition to full chip verification. You will run verification at block & chip level with various high-speed IPs integrated like ODSP, D2D IP, SerDes XSR, SerDes PAM4 integrated drivers/TIA, and control functions. You will develop functional coverage models, assertions, and debug complex verification issues within a UVM-based framework. Prior to tapeout you will run functional scenarios with CPU FW loaded and verify functionality at the CPU sub-system level. You may be involved in FPGA verification. Post Silicon you will be involved in ATE test plan and test vector generation, ATE testing and release to production.

  • Develop testbench components for Silicon Photonics subsystems. Proven ability to build UVM components (agents, drivers, monitors, scoreboards, sequences) and implement constrained-random and directed test strategies
  • Ability to understand coverage metrics and functional specifications
  • Understand and implement verification scenarios per full chip analog and digital verification test plans
  • Analyse coverage, add scenarios to enhance coverage and debug functional simulations, add corner verification cases and identify and resolve functional bugs
  • FW/C-Coding and verification of CPU sub-systems with FW
  • Must have good knowledge of Python and C. Develop scripts for automated analysis and reports
  • Good understanding of RTL digital design and DFT (Design for Test) principles
  • Excellent organizational, teamwork, and communication skills

Minimum Qualifications

  • Bachelor’s or Masters in Electronics Engineering (or equivalent/related)
  • 8-12 years of functional verification experience
  • Strong skills in SystemVerilog, Python, C and UVM methodology
  • Familiarity with UVM phases, configuration mechanisms, factory overrides, and reuse across block, subsystem, and SoC-level verification
  • Good understanding of CPU sub-systems, FPGA, ODSP & integrated transceiver features, SerDes, Ethernet, D2D PHY IP & Protocols
  • Experience with RTL design, simulation tools, (e.g., Synopsys, Cadence, Mentor Graphics) and ASIC design flow
  • You must be a team player and be able to drive decisions quickly with consensus building.
  • Strong analytical, problem-solving and debugging skills
  • Strong teamwork, communication, and organizational skills

Why Cisco?

At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.

Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.

We are Cisco, and our power starts with you.

How we rate this

ASIC Engineering Design Verification Leader (SystemVerilog, Python, C and UVM |8-12 years| Pune) at Cisco rates 0 out of 100 for how much of the daily work is AI. That makes it Little AI (AI Level 1 of 4). The level is about AI in the job, not seniority.

Classification

Little AI. AI is not part of the work.

  1. ●●●● Builds AI80 to 100
  2. ●●●○ Works on AI60 to 79
  3. ●●○○ Uses AI40 to 59
  4. ●○○○ Little AI0 to 39

Levels come from how often the tools, models and workflows of the role are named in the posting itself. Read the description and count the AI tools, models and workflows it names.

Prepare for this job

Built from this posting and from similar jobs on Level.

Skills and AI tools this role asks for

Asic VerificationChip VerificationTestbench DevelopmentFunctional CoverageDebuggingSystemVerilogPythonC

Questions you could be asked

  1. Tell me about a project where asic verification was part of your work. What did you do?
  2. Tell me about a project where chip verification was part of your work. What did you do?
  3. Tell me about a project where testbench development was part of your work. What did you do?
  4. Tell me about a project where functional coverage was part of your work. What did you do?
  5. Tell me about a project where debugging was part of your work. What did you do?

Adapt your resume

  • List these exact terms on your resume: Asic Verification, Chip Verification, Testbench Development, Functional Coverage, and Debugging. An applicant tracking system matches the wording, not the idea.
  • Attach one line of real, concrete experience to at least one of them. A tool named with nothing behind it rarely survives a human read.

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