Chassis IP Senior Design Engineer

Intel is hiring a Chassis IP Senior Design Engineer in Bengaluru, India. Level rates it ; you can apply on Intel.

Level's read on this job

On Level's scale, this role is Little AI ●○○○: aI is not part of the work.
Tools and skills the posting cites include Verilog, System Verilog and Amba.
Level classifies it as a senior role.
Level lists 826 other open roles at Intel.

AI in this role

Senior logic design engineer developing RTL code and architecture for SoC chassis interconnect IPs.

verilogsystem-verilogambapciecxl

logic-designrtl-codingsochardware-architecture

Job Details:

Job Description:

Intel is seeking an experienced Logic Design engineer for the Intel Chassis Group, which is chartered to deliver the chassis for SoCs within Intel. The role involves logic design of component and foundation IPs which can be used to build an SoC chassis. The ideal candidate will have strong design and Verilog skills and some background in protocol conversion bridges for AMBA/CXL protocols. Understanding of concepts such as QoS, access control, flow control, debug, RAS, security and error handling is a plus.

Key Responsibilities
- Develop logic designs, register transfer level (RTL) coding, and simulations required for functional units, IP blocks, and subsystems.
- Define and implement architecture and microarchitecture features for the interconnect IP block and sub-system which includes high-performance data plane and control plane routers, switches, arbiters, protocol conversion bridges, debug/trace components, and clock and power controls.
- Perform rigorous quality checks and optimization of RTL designs to improve IP power, performance, area, and timing, ensuring delivery of high-quality IP.
- Evaluate design trade-offs across area, bandwidth, timing, and reliability to achieve balanced and efficient IP functionality.
- Support Sub-system/SoC customers with high-quality IP integration and verification workflows.

Qualifications:

Minimum Qualifications
- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field, with a minimum of 10 years of experience in logic design and RTL development.
- Proficiency in Verilog/System Verilog and RTL coding.
- Expertise in AMBA (CHI, AXI, AHB, APB) and PCIe/CXL protocols.
- Experience with Lint/CDC/RDC tools and methodologies.
- Strong understanding of power, performance, Timing and area optimization strategies in complex designs.

Preferred Qualifications
- 5+ years of experience designing network components such as routers, switches, arbiters, or protocol conversion bridges.
- Knowledge of debug/trace networks, flow control, and hashing methodologies.
- Experience working with leading-edge semiconductor nodes.
- Background in DVFS (Dynamic Voltage Frequency Scaling) and UPF (Unified Power Format).
- Understanding of RAS (Reliability, Availability, and Serviceability) features.
- Proven ability to collaborate across geographically distributed teams and adapt to multi-time zone working environments.
- Familiarity with coherency concepts and memory subsystems.

Join Intel and contribute to transformative innovations in semiconductor design that shape the future of technology.

Job Type:

Experienced Hire

Shift:

Shift 1 (India)

Primary Location:

India, Bangalore

Additional Locations:

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

How we rate this

Chassis IP Senior Design Engineer at Intel rates 0 out of 100 for how much of the daily work is AI. That makes it Little AI (AI Level 1 of 4). The level is about AI in the job, not seniority.

Classification

Little AI. AI is not part of the work.

●●●● Builds AI80 to 100
●●●○ Works on AI60 to 79
●●○○ Uses AI40 to 59
●○○○ Little AI0 to 39

Levels come from how often the tools, models and workflows of the role are named in the posting itself. Read the description and count the AI tools, models and workflows it names.

Key facts

Chassis IP Senior Design Engineer is an open job at Intel.
Level rates this role AI Level 1 of 4: Little AI.
The role is based in India, Bangalore.
The job was posted on October 14, 2026.
Seniority: senior.
Applications are handled by Intel. Apply on Intel

Prepare for this job

Built from this posting and from similar jobs on Level.

Skills and AI tools this role asks for

Logic DesignRtl CodingSocHardware ArchitectureVerilogSystem VerilogAmbaPcie

Questions you could be asked

Tell me about a project where logic design was part of your work. What did you do?
Tell me about a project where rtl coding was part of your work. What did you do?
Tell me about a project where soc was part of your work. What did you do?
Tell me about a project where hardware architecture was part of your work. What did you do?
Walk me through how you've used Verilog in your day-to-day work.

Adapt your resume

List these exact terms on your resume: Logic Design, Rtl Coding, Soc, Hardware Architecture, and Verilog. An applicant tracking system matches the wording, not the idea.
Attach one line of real, concrete experience to at least one of them. A tool named with nothing behind it rarely survives a human read.

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