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Anduril Industries

FPGA Verification Engineer, Air Dominance and Strike

Anduril Industries is hiring an FPGA Verification Engineer, Air Dominance and Strike. It pays $146k-$194k a year and Level rates it ; you can apply on Anduril Industries.

Level's read on this job

  • On Level's scale, this role is Little AI ●○○○: aI is not part of the work.
  • The posting mentions SystemVerilog, UVM and Amd Xilinx among its tools and skills.
  • Level classes it as a mid-level role.
  • Anduril Industries has 2,500+ other open roles on Level.

AI in this role

Architect and implement UVM verification environments for flight-critical FPGA and SoC designs on AMD Xilinx platforms.

systemveriloguvmamd-xilinx
computer-visionfpga-verificationsoc-verificationconstrained-randomcoverage-driven-verificationdo-254

Anduril Industries is a defense technology company with a mission to transform U.S. and allied military capabilities with advanced technology. By bringing the expertise, technology, and business model of the 21st century’s most innovative companies to the defense industry, Anduril is changing how military systems are designed, built and sold. Anduril’s family of systems is powered by Lattice OS, an AI-powered operating system that turns thousands of data streams into a realtime, 3D command and control center. As the world enters an era of strategic competition, Anduril is committed to bringing cutting-edge autonomy, AI, computer vision, sensor fusion, and networking technology to the military in months, not years.

ABOUT THE JOB

We are looking for a FPGA Verification Engineer to join our rapidly growing team in Costa Mesa, CA. You will own verification of FPGA/SoC designs on AMD (Xilinx) platforms for flight-critical avionics, with a focus on UVM-based methodology and coverage-driven verification. This will require expertise in SystemVerilog, object-oriented programming, and UVM. If you are someone who has supported rapid avionics development, then this role is for you.

WHAT YOU’LL DO

  • Architect and implement UVM verification environments (drivers, monitors, predictors, scoreboards) for AMD (Xilinx) FPGA/SoC designs
  • Develop verification plans with traceability to system and hardware requirements
  • Author SystemVerilog Assertions (SVA) for protocol compliance and design intent checks
  • Build functional coverage models and drive code coverage analysis to closure
  • Develop constrained-random and transaction-level test sequences to maximize coverage and uncover corner-case bugs
  • Establish and maintain regression suites, tracking coverage metrics and verification progress
  • Debug failures using waveform tools and simulation logs at the HDL and system level
  • Collaborate with design engineers on RTL reviews, bug resolution, and micro-architecture refinement
  • Support hardware validation and board bring-up on target platforms
  • Ensure verification meets DO-254 and relevant safety standards
  • Author verification closure reports and coverage analysis summaries

REQUIRED QUALIFICATIONS

  • Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field
  • 2+ years of experience in FPGA/ASIC verification
  • Proficient in SystemVerilog, UVM methodology and SVA, with experience contributing to and extending UVM testbenches
  • Object-oriented programming principles
  • Industry simulators (Questa, VCS, Xcelium, or Vivado)
  • Git-based collaborative workflows including code review
  • Linux development environments
  • Strong communication and teamwork skills
  • Eligible to obtain and hold a U.S. Secret security clearance

PREFERRED QUALIFICATIONS

  • 5+ years of experience in FPGA/ASIC verification
  • Master’s degree in Electrical Engineering, Computer Engineering, or related field
  • DO-254, avionics verification standards for UAS, and safety-critical verification processes
  • SVUnit or equivalent unit-testing frameworks
  • Formal verification or CDC verification tools
  • Digital interfaces: Ethernet, PCIe, JESD204C, MIL-STD-1553, SPI
  • Verification automation scripting (Python, Tcl, Makefile)
  • SoC and ARM-based embedded platforms
  • Verification automation, CI/CD integration, and Nix-based build environments
US Salary Range$146,000—$194,000 USD

The salary range for this role is an estimate based on a wide range of compensation factors, inclusive of base salary only. Actual salary offer may vary based on (but not limited to) work experience, education and/or training, critical skills, and/or business considerations. Highly competitive equity grants are included in the majority of full time offers; and are considered part of Anduril's total compensation package. Additionally, Anduril offers top-tier benefits for full-time employees, including:

Benefits

At Anduril, we invest in our people. Our comprehensive, competitive benefits package (available at little to no cost to employees) ensures you’re supported in health, recovery, and whatever comes next. For more information, Explore Our Benefits.

Protecting Yourself from Recruitment Scams

Anduril is committed to maintaining the integrity of our Talent acquisition process and the security of our candidates. We've observed a rise in sophisticated phishing and fraudulent schemes where individuals impersonate Anduril representatives, luring job seekers with false interviews or job offers. These scammers often attempt to extract payment or sensitive personal information.

To ensure your safety and help you navigate your job search with confidence, please keep the following critical points in mind:

  • No Financial Requests: Anduril will never solicit payment or demand personal financial details (such as banking information, credit card numbers, or social security numbers) at any stage of our hiring process. Our legitimate recruitment is entirely free for candidates.

  • Please always verify communications:
    • Direct from Anduril: If you receive an email from one of our recruiters, it will only come from an @anduril.com address.
    • Via Agency Partner: If contacted by a recruiting agency for an Anduril role, their email will clearly identify their agency. If you suspect any suspicious activity, please verify the agency's authenticity by reaching out to contact@anduril.com.
  • Exercise Caution with Unsolicited Outreach: If you receive any communication that appears suspicious, contains grammatical errors, or makes unusual requests, do not engage. Always confirm the sender's email domain is @anduril.com before providing any personal information or clicking on links.

  • What to Do If You Suspect Fraud: Should you encounter any questionable or fraudulent outreach claiming to be from Anduril, please report it immediately to contact@anduril.com. Your proactive caution is invaluable in protecting your personal information and upholding the security and trustworthiness of our recruitment efforts.

Data Privacy

To view Anduril's candidate data privacy policy, please visit https://anduril.com/applicant-privacy-notice/.

By submitting your application, you consent to Anduril Industries using a third-party service provider to conduct pre-employment risk, integrity, and due diligence screening and assessing potential risks as part of your application process. This third-party service provider provides risk-intelligence services that may include analysis of sanctions and watchlists, adverse media, public-record information, and other lawful open-source or commercial data sources. This third-party service provider does not act as a consumer reporting agency. Use of this provider helps to ensure compliance with applicable laws and protect technology, intellectual property, and organizational security.

How we rate this

FPGA Verification Engineer, Air Dominance and Strike at Anduril Industries rates 10 out of 100 for how much of the daily work is AI. That makes it Little AI (AI Level 1 of 4). The level is about AI in the job, not seniority.

Classification

Little AI. AI is not part of the work.

  1. ●●●● Builds AI80 to 100
  2. ●●●○ Works on AI60 to 79
  3. ●●○○ Uses AI40 to 59
  4. ●○○○ Little AI0 to 39

Levels come from how often the tools, models and workflows of the role are named in the posting itself. Read the description and count the AI tools, models and workflows it names.

Prepare for this job

Built from this posting and from similar jobs on Level.

Skills and AI tools this role asks for

Computer visionFPGA VerificationSoc VerificationConstrained RandomCoverage Driven VerificationDo 254SystemVerilogUVM

Questions you could be asked

  1. Walk me through a computer vision problem you solved, from raw data to a deployed model.
  2. Tell me about a project where fpga verification was part of your work. What did you do?
  3. Tell me about a project where soc verification was part of your work. What did you do?
  4. Tell me about a project where constrained random was part of your work. What did you do?
  5. Tell me about a project where coverage driven verification was part of your work. What did you do?

Adapt your resume

  • List these exact terms on your resume: Computer vision, FPGA Verification, Soc Verification, Constrained Random, and Coverage Driven Verification. An applicant tracking system matches the wording, not the idea.
  • Attach one line of real, concrete experience to at least one of them. A tool named with nothing behind it rarely survives a human read.

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