IP RTL Design Engineer

Samsung Electronics is hiring an IP RTL Design Engineer in Bengaluru, India. Level rates it ; you can apply on Samsung Electronics.

Level's read on this job

On Level's scale, this role is Little AI ●○○○: aI is not part of the work.
The posting mentions Verilog, SystemVerilog and rtl design among its tools and skills.
Level classes it as a mid-level role.
Samsung Electronics has 617 other open roles on Level.

AI in this role

Design and maintain synthesizable RTL for high-speed memory PHY blocks and support silicon validation at Samsung.

verilogsystemverilog

rtl-designasic-designsynthesissta

Position Summary

About Samsung Semiconductor India Research (SSIR)With a wide range of industry-leading semiconductor solutions, we are enabling innovative growth in market segments in component solutions, featuring industry-leading technologies in System LSI, Memory and Foundry. Our engineers are offered a foundation to work on cutting-edge technologies such as Foundation IP Design, Mobile SoCs, Storage Solutions, AI/ML, 5G/ 6G solutions, Neural processors, Serial Interfaces, Multimedia IPs and much more. As one of the largest R&D centers outside Korea for Samsung Electronics, we take pride in our ability to work on some of the cutting edge technologies. Our engineers get to work across diverse domains, projects, products, clients, people and countries, and conduct research in new and emerging technology areas. Innovation and creativity are highly valued at this innovation hub, as we strive towards providing high reliability; high performance and value added services that enable Samsung Electronics deliver world-class products.

Role and Responsibilities

Samsung Semiconductor India Research (SSIR) is seeking an experienced RTL/Logic Design Engineer to join the Memory PHY IP development team. The role will focus on the development of HBM, LPDDR PHY projects, delivering high‑performance PHY IP for our customers and providing post‑silicon support.

Write, verify, and maintain synthesizable RTL for LPDDR PHY blocks

- Write SDC constraints, synthesize and ensure timing closure.

- Setup and run IPXACT, LINT, CDC, SDC, PreSTA, DFT and ATPG checks

- Support silicon validation bring-up and debug post-silicon issues

- Work closely with internal and external customers to understand requirements and timely deliverables

Required Qualifications:

- 4 years of full‑cycle RTL/logic design experience, preferably in memory‑PHY or high‑speed interface IP.

- Strong RTL coding background (Verilog/SystemVerilog)

- Proficiency with QC tools such as LINT, CDC, DFT, ATPG

- Experience in SDC creation, Synthesis & STA

- Prior work on LPDDR, HBM PHY projects is preferred

Skills and Qualifications

Experience – 4 to 10 Years of experience

Qualifications

B.Tech/B.E/M.Tech/M.E

Disclaimer

Samsung Semiconductor India Research (SSIR), a division of Samsung R&D India - Bangalore Pvt. Ltd is dedicated to employing a diverse workforce and providing Equal Employment Opportunity to all individuals, regardless of their religion, gender, age, marital status, gender identity, status as a protected veteran, genetic information, status as a qualified individual with a disability, or any other characteristic protected by law.

* Please visit Samsung membership to see Privacy Policy, which defaults according to your location. You can change Country/Language at the bottom of the page. If you are European Economic Resident, please click here.

How we rate this

IP RTL Design Engineer at Samsung Electronics rates 0 out of 100 for how much of the daily work is AI. That makes it Little AI (AI Level 1 of 4). The level is about AI in the job, not seniority.

Classification

Little AI. AI is not part of the work.

●●●● Builds AI80 to 100
●●●○ Works on AI60 to 79
●●○○ Uses AI40 to 59
●○○○ Little AI0 to 39

Levels come from how often the tools, models and workflows of the role are named in the posting itself. Read the description and count the AI tools, models and workflows it names.

Key facts

IP RTL Design Engineer is an open job at Samsung Electronics.
Level rates this role AI Level 1 of 4: Little AI.
The role is based in SSIR, Goldstone, Bangalore, India.
The job was posted on May 18, 2026.
Seniority: mid.
Applications are handled by Samsung Electronics. Apply on Samsung Electronics

Prepare for this job

Built from this posting and from similar jobs on Level.

Skills and AI tools this role asks for

Rtl DesignAsic DesignSynthesisStaVerilogSystemVerilog

Questions you could be asked

Tell me about a project where rtl design was part of your work. What did you do?
Tell me about a project where asic design was part of your work. What did you do?
Tell me about a project where synthesis was part of your work. What did you do?
Tell me about a project where sta was part of your work. What did you do?
Walk me through how you've used Verilog in your day-to-day work.

Adapt your resume

List these exact terms on your resume: Rtl Design, Asic Design, Synthesis, Sta, and Verilog. An applicant tracking system matches the wording, not the idea.
Attach one line of real, concrete experience to at least one of them. A tool named with nothing behind it rarely survives a human read.

Want an expert to read your CV for this job?

Free. Send your CV and the role you want next. You get your review by email within 24 hours.

Get a free CV review Get your CV rewritten Check your resume with the ATS resume checker