Principal Engineer, Project Management - Chip Design

NVIDIA is hiring a Principal Engineer, Project Management - Chip Design in Tel Aviv, Israel. Level rates it ; you can apply on NVIDIA.

Level's read on this job

Little AI ●○○○ is how Level rates this project manager role: aI is not part of the work.
Tools and skills the posting cites include Verilog, System Verilog and UVM.
Level classifies it as a lead role.
Level lists 2,700+ other open roles at NVIDIA.

AI in this role

Lead the pre-silicon development and lifecycle management of advanced switch ASICs from concept to mass production.

verilogsystem-veriloguvm

asic-designproject-managementrtl-designsoc-integrationchip-design

NVIDIA Switches ASIC group is seeking a top-tier ASIC technical manager to lead the development of our next-generation ASICs. Join us in shaping the future of technology! As an ASIC Project Lead, you will manage the pre-silicon development activities of NVIDIA's most advanced and complex switch ASICs. From concept to tape-out and from chip power-on to mass production, you will be the driving force behind the entire lifecycle of our ASIC projects. You will collaborate with a cross-disciplinary team, interacting with unit-level ASIC, Physical Design, CAD, Package Design, Firmware & Software, DFT, System Design, Analog Design, and other specialized teams.

What you’ll be doing:

Lead the ASIC development from concept and architecture stages through micro-architecture, design, verification, and physical design until tape-out.
Post-Silicon Activities; Oversee chip power-on, bring-up, quality phases, and mass production.
Execution Plans; Define and implement execution plans in collaboration with cross-discipline leaders in unit level, full-chip, physical design, and firmware/software emulation.
Roadmap Definition; Contribute to the definition of NVIDIA's switch ASIC roadmap.

What we need to see:

BS or MS in Computer or Electrical Engineering or equivalent experience.
15+ overall years of proven experience in chip design.
8+ years of experience in chip design/verification management, leading teams of at least 8 direct reports.
Proficiency in RTL design (Verilog), verification (UVM, System Verilog), System-On-Chip design/integration flow, and design automation.
High system view with ability to collaborate with multiple interfaces.
Strong analytical and problem-solving skills.
Excellent communication and teamwork abilities.
Experience in synthesis, and physical design is a plus.

If you are creative, autonomous, and love a challenge, we want to hear from you! Join NVIDIA and be a part of the team that is driving the future of technology.

NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.

How we rate this

Principal Engineer, Project Management - Chip Design at NVIDIA rates 10 out of 100 for how much of the daily work is AI. That makes it Little AI (AI Level 1 of 4). The level is about AI in the job, not seniority.

Classification

Little AI. AI is not part of the work.

●●●● Builds AI80 to 100
●●●○ Works on AI60 to 79
●●○○ Uses AI40 to 59
●○○○ Little AI0 to 39

Levels come from how often the tools, models and workflows of the role are named in the posting itself. Read the description and count the AI tools, models and workflows it names.

Key facts

Principal Engineer, Project Management - Chip Design is an open job at NVIDIA.
Level rates this role AI Level 1 of 4: Little AI.
The role is based in Israel, Tel Aviv.
The job was posted on August 10, 2026.
Seniority: lead.
Applications are handled by NVIDIA. Apply on NVIDIA

Prepare for this job

Built from this posting and from similar jobs on Level.

Skills and AI tools this role asks for

Asic DesignProject ManagementRtl DesignSoc IntegrationChip DesignVerilogSystem VerilogUVM

Also common in project manager jobs at this level

AWS SQL Azure Generative AI Machine learning Python

Pay

Typical project manager job: $111k

This posting doesn't list pay. Use the typical project manager figure when pay comes up. See project manager jobs

Questions you could be asked

Tell me about a project where asic design was part of your work. What did you do?
Tell me about a project where project management was part of your work. What did you do?
Tell me about a project where rtl design was part of your work. What did you do?
Tell me about a project where soc integration was part of your work. What did you do?
Tell me about a project where chip design was part of your work. What did you do?

Adapt your resume

List these exact terms on your resume: Asic Design, Project Management, Rtl Design, Soc Integration, and Chip Design. An applicant tracking system matches the wording, not the idea.
Attach one line of real, concrete experience to at least one of them. A tool named with nothing behind it rarely survives a human read.

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