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Etched

Product Engineer, Silicon Validation

Etched is hiring a Product Engineer, Silicon Validation in San Jose, United States. Level rates it ; you can apply on Etched.

Level's read on this job

  • On Level's scale, this role is Works on AI ●●●○: the daily work is on AI products, without building the model.
  • The posting mentions Ate, Slt and Python among its tools and skills.
  • Level classes it as a senior role.
  • Etched has 114 other open roles on Level.

AI in this role

Lead silicon validation and test program development for large-format AI accelerator chips to ensure production quality and performance.

AteSltPython
silicon-validationtest-program-developmentyield-optimizationhardware-testing

About Etched

Etched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first products are heavily focused on inference. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.

Job Summary

We are seeking an experienced Product Engineer to lead silicon validation, test program

development, and productization for our large-format AI accelerator chips. In this role, you will develop and execute test strategies from first silicon through high-volume manufacturing, partnering with cross-functional teams and external vendors to ensure production quality and cost targets. This role is critical to achieving first-pass silicon success and seamless NPI-to-HVM transitions.

Key Responsibilities

  • Planning and executing comprehensive silicon characterization from first silicon through production release, including voltage-frequency-temperature characterization, corner testing, guard band determination, and production limit setting

  • Lead test cost optimization efforts while maintaining quality standards

  • Architect test flows to balance test time, coverage, and yield learning objectives for complex AI accelerator designs

  • Drive systematic yield improvement initiatives through data-driven root cause analysis using statistical tools and methods

  • Establish and track key quality metrics including DPPM and test escapes

  • Perform die/package level bring-ups, troubleshoot failure modes, and resolve issues by collaborating with design, system validation, and operations teams

  • Support OSAT bring-up, manage ATE/SLT manufacturing test program releases, and drive toward aggressive test cost goals

  • Productize test programs and methodologies for seamless transition from engineering to high-volume manufacturing

  • Analyze field return data and system-level failures to identify test coverage gaps and implement improved screening methods

  • Drive ATE-system correlation activities to ensure test program accuracy and validate performance against system specs

  • Manage relationships with test vendors, OSAT partners, and foundry partners

You may be a good fit if you have (Must-have qualifications)

  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field

  • 5-10+ years of hands-on experience in silicon validation, product engineering, and ATE test development for advanced node semiconductors

  • Proven track record in yield optimization and DPPM reduction with quantifiable results

  • Experience with silicon characterization methodologies including Fmax/Vmin characterization and power/thermal validation

  • High-volume manufacturing test experience with demonstrated production scale results

  • Proficiency in yield and fail pareto analysis using JMP, Exensio, DataPower, or OptimalPlus

  • Strong understanding of test program debugging, failure analysis correlation, and yield enhancement techniques

Strong candidates may also have experience with (Nice-to-have qualifications)

  • Experience developing and optimizing ATE test programs for wafer sort and final test on

    Advantest V93K platforms

  • Experience managing wafer sort and final test across multiple advanced process nodes

  • GPU, HPC, or AI accelerator chip testing background with production scale results

  • HBM or high-speed memory interface testing and characterization experience

  • Leading NPI through high-volume production with multi-vendor qualification across multiple OSAT sites

  • Driving significant cost reduction initiatives

  • Multi-site parallel testing strategies and test time optimization for large-format dies

  • Scripting and automation skills (Python, Perl, TCL) for test data analysis and workflow automation

  • Cross-functional leadership in silicon bring-up and manufacturing ramp

Benefits

  • Medical, dental, and vision packages with generous premium coverage

    • $500 per month credit for waiving medical benefits

  • Housing subsidy of $2.5k per month for those living within walking distance of the office

  • Relocation support for those moving to San Jose (Santana Row)

  • Various wellness benefits covering fitness, mental health, and more

  • Daily lunch and dinner in our office

  • Unlimited compute budget subject to ROI justification

How we’re different

Etched believes in the Bitter Lesson. We are the first inference-focused frontier AI system. Our addressable market is the entirety of inference, unlike many of our competitors.

We are a fully in-person team in San Jose (Santana Row), and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both and work across disciplines as needed.

How we rate this

Product Engineer, Silicon Validation at Etched rates 60 out of 100 for how much of the daily work is AI. That makes it Works on AI (AI Level 3 of 4). The level is about AI in the job, not seniority.

Classification

Works on AI. The daily work is on AI products, without building the model.

  1. ●●●● Builds AI80 to 100
  2. ●●●○ Works on AI60 to 79
  3. ●●○○ Uses AI40 to 59
  4. ●○○○ Little AI0 to 39

Levels come from how often the tools, models and workflows of the role are named in the posting itself. Read the description and count the AI tools, models and workflows it names.

Prepare for this job

Built from this posting and from similar jobs on Level.

Skills and AI tools this role asks for

Silicon ValidationTest Program DevelopmentYield OptimizationHardware TestingAteSltPython

Questions you could be asked

  1. Tell me about a project where silicon validation was part of your work. What did you do?
  2. Tell me about a project where test program development was part of your work. What did you do?
  3. Tell me about a project where yield optimization was part of your work. What did you do?
  4. Tell me about a project where hardware testing was part of your work. What did you do?
  5. Walk me through how you've used Ate in your day-to-day work.

Adapt your resume

  • List these exact terms on your resume: Silicon Validation, Test Program Development, Yield Optimization, Hardware Testing, and Ate. An applicant tracking system matches the wording, not the idea.
  • Attach one line of real, concrete experience to at least one of them. A tool named with nothing behind it rarely survives a human read.
  • Show where AI is part of your daily process, not a one-off project. This role expects it to be a running habit.

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