Senior ASIC Timing Engineer, DFT

NVIDIA is hiring a Senior ASIC Timing Engineer, DFT in Santa Clara, United States. Level rates it ; you can apply on NVIDIA.

Level's read on this job

On Level's scale, this role is Little AI ●○○○: aI is not part of the work.
Tools and skills the posting cites include static timing analysis, dft and timing closure.
Level classifies it as a senior role.
Level lists 2,700+ other open roles at NVIDIA.
The role was posted in the last few days.

AI in this role

Drive timing analysis and closure for DFT logic across hierarchical levels on NVIDIA chips.

static-timing-analysisdfttiming-closureecosasic

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world.

NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities which are hard to solve, that only we can pursue, and that matter to the world. This is our life’s work, to amplify human inventiveness and intelligence. Our team has some of the most forward-thinking and hardworking people in the world. We are now looking for a motivated DFT-Timing Engineer to join our dynamic and growing team. If you want to challenge yourself and be a part of something great, join us today!

What you'll be doing:

Drive timing analysis and closure for DFT logic on all Nvidia chips (GPUs/CPUs/DPUs/LPUs/SoCs) at all hierarchical levels (block/cluster/full-chip).
Work with PD, DFX, Clocks and other teams to come up with timing closure strategy, develop timing constraints for custom DFT designs, drive timing and power convergence, and implement ECOs.
Continuously improve workflows and designs by introducing more automation, resilience, and standardization.

What we need to see:

BS (or equivalent experience) in Electrical or Computer Engineering with 5+ years’ experience or MS (or equivalent experience) with 2+ years’ experience.
Hands-on experience in Static Timing Analysis (STA) and driving timing convergence at full-chip/sub-chip level in advanced technology nodes.
Expertise in analysis and fixing of timing paths through ECOs.
Expertise in developing timing constraints.
In-depth knowledge of industry standard timing convergence tools.

Ways to stand out from the crowd:

Understanding of DFT logic and experience with DFT timing closure for various modes e.g., scan, iJTAG, etc.
Background in domain specific STA and timing convergence, such as Serdes, Processor, IO, SMVA, etc.
Experience in methodology and/or workflow development.

NVIDIA is widely considered to be the leader of AI computing, and one of the technology world’s most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us. If you're creative and autonomous, we want to hear from you.

You will also be eligible for equity and benefits.

Applications for this job will be accepted at least until November 6, 2026.

This posting is for an existing vacancy.

NVIDIA uses AI tools in its recruiting processes.

NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.

How we rate this

Senior ASIC Timing Engineer, DFT at NVIDIA rates 0 out of 100 for how much of the daily work is AI. That makes it Little AI (AI Level 1 of 4). The level is about AI in the job, not seniority.

Classification

Little AI. AI is not part of the work.

●●●● Builds AI80 to 100
●●●○ Works on AI60 to 79
●●○○ Uses AI40 to 59
●○○○ Little AI0 to 39

Levels come from how often the tools, models and workflows of the role are named in the posting itself. Read the description and count the AI tools, models and workflows it names.

Key facts

Senior ASIC Timing Engineer, DFT is an open job at NVIDIA.
Level rates this role AI Level 1 of 4: Little AI.
The role is based in US, CA, Santa Clara.
The job was posted on November 2, 2026.
Seniority: senior.
Applications are handled by NVIDIA. Apply on NVIDIA

Prepare for this job

Built from this posting and from similar jobs on Level.

Skills and AI tools this role asks for

Static Timing AnalysisDftTiming ClosureEcosAsic

Questions you could be asked

Tell me about a project where static timing analysis was part of your work. What did you do?
Tell me about a project where dft was part of your work. What did you do?
Tell me about a project where timing closure was part of your work. What did you do?
Tell me about a project where ecos was part of your work. What did you do?
Tell me about a project where asic was part of your work. What did you do?

Adapt your resume

List these exact terms on your resume: Static Timing Analysis, Dft, Timing Closure, Ecos, and Asic. An applicant tracking system matches the wording, not the idea.
Attach one line of real, concrete experience to at least one of them. A tool named with nothing behind it rarely survives a human read.

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