Senior ASIC Verification Engineer - Networking Chip Design

NVIDIA is hiring a Senior ASIC Verification Engineer - Networking Chip Design in Shanghai, China. Level rates it ; you can apply on NVIDIA.

Level's read on this job

On Level's scale, this role is Little AI ●○○○: aI is not part of the work.
Tools and skills the posting cites include SystemVerilog, UVM and asic verification.
Level classifies it as a senior role.
Level lists 2,700+ other open roles at NVIDIA.

AI in this role

Perform fullchip verification and maintain test environments for high-speed networking switch silicon chips.

systemveriloguvm

asic-verificationchip-designtest-planningdebuggingregression-testing

We are now looking for Fullchip Verification Enginneer for the Networking Switch Chip Design Group.

As a Engineer at NVIDIA's Networking Chip Design Group, you'll join a group of passionate engineers to deliver the next generation state of the art Switch Silicon chips. In this position, you'll make a real impact in a dynamic, technology-focused company while developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency!

What you'll be doing:

Work in a combined design and verification team specializing in Switch Fullchip works
Understand the Switch architecture and build on testplan accordingly
Maintain and optimize Fullchip verification enviornment to meet feature requirements efficiently
Develop Fullchip test suites, maintain regressions, debug failures and sign-off coverages

What we need to see:

Electrical Engineering B.Sc. or Computer Engineering B.Sc. graduate with high scores or equivalent experience.
5+ years of experience in DV relevant works
A team player with good communication and interpersonal skills.
Previous experience in full chip verification enviornment for complex chips – an advantage.

NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us. Are you creative and autonomous? Do you love the challenge of crafting the highest performance & lowest power silicon possible? If so, we want to hear from you. Come, join our Switch Silicon design team and help us build the next chip in this exciting and quickly growing field

How we rate this

Senior ASIC Verification Engineer - Networking Chip Design at NVIDIA rates 0 out of 100 for how much of the daily work is AI. That makes it Little AI (AI Level 1 of 4). The level is about AI in the job, not seniority.

Classification

Little AI. AI is not part of the work.

●●●● Builds AI80 to 100
●●●○ Works on AI60 to 79
●●○○ Uses AI40 to 59
●○○○ Little AI0 to 39

Levels come from how often the tools, models and workflows of the role are named in the posting itself. Read the description and count the AI tools, models and workflows it names.

Key facts

Senior ASIC Verification Engineer - Networking Chip Design is an open job at NVIDIA.
Level rates this role AI Level 1 of 4: Little AI.
The role is based in China, Shanghai.
The job was posted on August 5, 2026.
Seniority: senior.
Applications are handled by NVIDIA. Apply on NVIDIA

Prepare for this job

Built from this posting and from similar jobs on Level.

Skills and AI tools this role asks for

Asic VerificationChip DesignTest PlanningDebuggingRegression TestingSystemVerilogUVM

Questions you could be asked

Tell me about a project where asic verification was part of your work. What did you do?
Tell me about a project where chip design was part of your work. What did you do?
Tell me about a project where test planning was part of your work. What did you do?
Tell me about a project where debugging was part of your work. What did you do?
Tell me about a project where regression testing was part of your work. What did you do?

Adapt your resume

List these exact terms on your resume: Asic Verification, Chip Design, Test Planning, Debugging, and Regression Testing. An applicant tracking system matches the wording, not the idea.
Attach one line of real, concrete experience to at least one of them. A tool named with nothing behind it rarely survives a human read.

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