Sr. Formal Verification Engineer, Amazon Leo

Amazon is hiring a Sr. Formal Verification Engineer, Amazon Leo in Austin, United States. It pays $185k-$250k a year and Level rates it ; you can apply on Amazon.

Level's read on this job

Level rates this role Little AI ●○○○: aI is not part of the work.
The posting mentions Jaspergold, Questa Formal and SystemVerilog among its tools and skills.
Level classes it as a senior role.
Amazon has 20,000+ other open roles on Level.

AI in this role

Senior Formal Verification Engineer needed to drive formal verification for modem SoCs, integrating AI-centric verification methodologies.

jaspergoldquesta-formalsystemverilog

formal-verificationsoc-designhardware-verification

Amazon's Leo Silicon Team is building next-generation modem SoCs for broadband
communication, a constellation of low Earth orbit satellites designed to deliver fast, affordable broadband to unserved and underserved communities around the world. Our Design Verification team is seeking a highly skilled and motivated Senior Formal Verification Engineer to drive formal verification efforts across our complex modem SoC designs.

In this role, you will apply rigorous mathematical methods to prove design correctness and
uncover corner-case bugs that escape simulation-based verification. You will serve as a subject matter expert in formal verification methodologies, mentor engineers across the team, and collaborate closely with RTL designers, simulation-based DV engineers, emulation engineers, and architects to shift verification left and improve overall silicon quality. This is a high-impact role on a team that is scaling verification capabilities with each successive tape-
out and actively integrating AI-centric verification methodologies.

Export Control Requirement:
Due to applicable export control laws and regulations, candidates must be a U.S. citizen or national, U.S. permanent resident (i.e., current Green Card holder), or lawfully admitted into the U.S. as a refugee or granted asylum.

Key job responsibilities
● Develop and execute formal verification strategies using JasperGold and/or Questa
Formal for property checking (FPV), connectivity checking (CC), register verification,
and sequential equivalence checking (SEQ)
● Write, review, and debug SystemVerilog Assertions (SVA) — including assumptions,
assertions, and cover properties — to verify complex modem SoC design behaviors
across NOC, interconnect, modem IPs and control logic
● Drive convergence on formal proofs by applying abstraction techniques, complexity
reduction strategies, and assume-guarantee reasoning
● Collaborate with RTL designers, architects, and simulation-based DV engineers to
define verification plans that incorporate formal methods alongside UVM-based
simulation and emulation approaches
● Champion a "formal-first" verification strategy by identifying and pursuing
opportunities to apply formal verification to new design blocks — building on our
established formal verification checklist deployed across SoC and NoC partitions
● Develop reusable formal verification infrastructure, including constraint libraries,
parameterized property templates, and automated regression flows integrated into our
CI/CD verification pipeline
● Contribute to coverage closure strategies by leveraging formal coverage analysis to
complement simulation-driven functional coverage
● Mentor and guide DV engineers in formal verification techniques, SVA best practices,
and proof convergence strategies
● Partner with EDA vendors to evaluate new formal verification capabilities and drive
tool improvements that benefit the team

Basic qualifications

- Bachelor's degree in electrical engineering, computer engineering, or equivalent
- 8+ years of experience in ASIC/SoC design verification with a strong focus on formal verification
- Experience with JasperGold and/or Questa Formal
- Strong proficiency in SystemVerilog Assertions (SVA) and formal property specification
- Experience with formal verification applications: FPV, connectivity checking, register verification, equivalence checking, and coverage analysis
- Demonstrated ability to drive proof convergence on complex designs using abstraction, case-splitting, and assume-guarantee techniques
- Proficiency in SystemVerilog and UVM concepts
- Proficiency in leveraging AI/LLM tools to accelerate formal verification workflows including AI-assisted SVA generation, property debugging, proof exploration, and automated constraint refinement

Preferred qualifications

- Master's or PhD in Electrical Engineering, Computer Engineering, or a related field with a focus on formal methods
- Experience verifying complex SoC designs including NoC/interconnect fabrics, memory subsystems, or communication protocol logic
- Familiarity with modem/PHY/DSP architectures or satellite communications systems
- Experience with scripting languages (Python, TCL, Perl) for flow automation and regression management
- Track record of finding critical silicon bugs using formal methods that escaped simulation
- Experience integrating formal verification into continuous integration (CI) workflows
- Familiarity with emulation-based verification and how formal methods complement emulation strategies
- Strong written and verbal communication skills with the ability to influence cross- functional teams

Amazon is an equal opportunity employer and does not discriminate on the basis of protected veteran status, disability, or other legally protected status.

Los Angeles County applicants: Job duties for this position include: work safely and cooperatively with other employees, supervisors, and staff; adhere to standards of excellence despite stressful conditions; communicate effectively and respectfully with employees, supervisors, and staff to ensure exceptional customer service; and follow all federal, state, and local laws and Company policies. Criminal history may have a direct, adverse, and negative relationship with some of the material job duties of this position. These include the duties and responsibilities listed above, as well as the abilities to adhere to company policies, exercise sound judgment, effectively manage stress and work safely and respectfully with others, exhibit trustworthiness and professionalism, and safeguard business operations and the Company’s reputation. Pursuant to the Los Angeles County Fair Chance Ordinance, we will consider for employment qualified applicants with arrest and conviction records.

Our inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit https://amazon.jobs/content/en/how-we-hire/accommodations for more information. If the country/region you’re applying in isn’t listed, please contact your Recruiting Partner.

The base salary range for this position is listed below. Your Amazon package will include sign-on payments and restricted stock units (RSUs). Final compensation will be determined based on factors including experience, qualifications, and location. Amazon also offers comprehensive benefits including health insurance (medical, dental, vision, prescription, Basic Life & AD&D insurance and option for Supplemental life plans, EAP, Mental Health Support, Medical Advice Line, Flexible Spending Accounts, Adoption and Surrogacy Reimbursement coverage), 401(k) matching, paid time off, and parental leave. Learn more about our benefits at https://amazon.jobs/en/benefits.

USA, CA, San Diego - 185,200.00 - 250,000.00 USD annually
USA, CA, Sunnyvale - 213,000.00 - 287,500.00 USD annually
USA, TX, Austin - 185,200.00 - 250,000.00 USD annually
USA, WA, Redmond - 185,200.00 - 250,000.00 USD annually

How we rate this

Sr. Formal Verification Engineer, Amazon Leo at Amazon rates 20 out of 100 for how much of the daily work is AI. That makes it Little AI (AI Level 1 of 4). The level is about AI in the job, not seniority.

Classification

Little AI. AI is not part of the work.

●●●● Builds AI80 to 100
●●●○ Works on AI60 to 79
●●○○ Uses AI40 to 59
●○○○ Little AI0 to 39

Levels come from how often the tools, models and workflows of the role are named in the posting itself. Read the description and count the AI tools, models and workflows it names.

Key facts

Sr. Formal Verification Engineer, Amazon Leo is an open job at Amazon.
Level rates this role AI Level 1 of 4: Little AI.
The listed salary is $185k-$250k a year.
The role is based in US, TX, Austin.
The job was posted on August 26, 2026.
Seniority: senior.
Applications are handled by Amazon. Apply on Amazon

Prepare for this job

Built from this posting and from similar jobs on Level.

Skills and AI tools this role asks for

Formal VerificationSoc DesignHardware VerificationJaspergoldQuesta FormalSystemVerilog

Questions you could be asked

Tell me about a project where formal verification was part of your work. What did you do?
Tell me about a project where soc design was part of your work. What did you do?
Tell me about a project where hardware verification was part of your work. What did you do?
What's a project where you used Jaspergold hands-on?
Walk me through how you've used Questa Formal in your day-to-day work.

Adapt your resume

List these exact terms on your resume: Formal Verification, Soc Design, Hardware Verification, Jaspergold, and Questa Formal. An applicant tracking system matches the wording, not the idea.
Attach one line of real, concrete experience to at least one of them. A tool named with nothing behind it rarely survives a human read.

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