Sr. Substrates Development and Ramp Engineer

Intel is hiring a Sr. Substrates Development and Ramp Engineer in Taipei, Taiwan. Level rates it ; you can apply on Intel.

Level's read on this job

Little AI ●○○○ is how Level rates this role: aI is not part of the work.
Level classes it as a senior role.
Intel has 826 other open roles on Level.

AI in this role

Job Details:

Job Description:

Supports management/senior leadership to incorporate process and quality improvements in Intel's supply chain and logistics strategy.
Defines material inspection methodology, conducts studies related to cost control, process control, and production yield, and implements plans and programs to optimize supply chain.
Supports product long range plan development by defining next generation methodology capabilities to support Intel's supply chain roadmap.
Explores and benchmarks emerging technology in the industry. Contributes to Intel's future technology definition and requirements. Highlights gaps between roadmap strategy, manufacturing capability, and market demands and recommends solutions to addresses those gaps.
Tracks supply demand trends, conducts root cause analysis to find opportunities for process and quality improvements, and collaborates with supply chain leads to implement solutions.
Leads supplier selections for new business in partnership with commodity managers and technical/quality partners and drives product and purchase specification content to ensure commodity performance compliance.
Performs alternate sourcing risk mitigation for single sourced commodities.
Establishes control standards, determines KPIs, monitors performance against targets, and drives root cause analysis for supply chain issues to arrive at solutions.
Drives supplier process window validation activities on critical process modules through all stages of development.
Drives supplier improvements on quality, reliability, yield, and cost.
Maintains quality standards and systems, creating relevant specifications to minimize variability and subjectivity to align with operational capability requirements.
Leads quality excursion management and drives failure mode analysis with suppliers.

Qualifications:

BS, MS or PhD in science or engineering fields with minimum 8 years of experience in semiconductor (Fab, Substrate, Assembly) development or manufacturing environment is required.
Strong skill required for supplier management, quality management, analytical problem solving, and influence in relevant fields of HVM.
In-depth knowledge required on substrate manufacturing processes and operations, raw materials, packaging technologies, and quality and process control system.
Fluent communication and articulation skills in business level English, strong presentation skills and ability to effectively communicate and interact with internally and supplier's management highly required.
Strong ability to work in cross functional teams are required.

Job Type:

Experienced Hire

Shift:

Shift 1 (Taiwan)

Primary Location:

Taiwan, Taipei

Additional Locations:

Business group:

Intel Foundry strives to make every facet of semiconductor manufacturing state-of-the-art while delighting our customers -- from delivering cutting-edge silicon process and packaging technology leadership for the AI era, enabling our customers to design leadership products, global manufacturing scale and supply chain, through the continuous yield improvements to advanced packaging all the way to final test and assembly. We ensure our foundry customers' products receive our utmost focus in terms of service, technology enablement and capacity commitments. Employees in the Foundry Technology Manufacturing are part of a worldwide factory network that designs, develops, manufactures, and assembly/test packages the compute devices to improve the lives of every person on Earth.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

How we rate this

Sr. Substrates Development and Ramp Engineer at Intel rates 38 out of 100 for how much of the daily work is AI. That makes it Little AI (AI Level 1 of 4). The level is about AI in the job, not seniority.

Classification

Little AI. AI is not part of the work.

●●●● Builds AI80 to 100
●●●○ Works on AI60 to 79
●●○○ Uses AI40 to 59
●○○○ Little AI0 to 39

Levels come from how often the tools, models and workflows of the role are named in the posting itself. Read the description and count the AI tools, models and workflows it names.